(no commit message)

diff --git a/openpower/sv/svp64_quirks.mdwn b/openpower/sv/svp64_quirks.mdwn
index 44b70792dfc52a60a28d73ace634cc325964c1ed..b8a862bab6bd65a9a40e2b40c3be55f8276c9f8b 100644 (file)
--- a/openpower/sv/svp64_quirks.mdwn
+++ b/openpower/sv/svp64_quirks.mdwn
@@ -614,7 +614,7 @@ Pack/Unpack has to be deployed across SVP64 sparingly (not so uniformly
 general) due to the fact that it takes up two RM.EXTRA bits, putting
 pressure on developers by restricting the register range as above.
 
-# LD/ST with zero-immediate
+# LD/ST with zero-immediate vs mapreduce mode
 
 LD/ST operations with a zero immediate effectively means that on a
 Vector operation the element index to offset the memory location is
@@ -626,7 +626,7 @@ that Power ISA has cache-inhibited LD/STs, for accessing memory-mapped
 peripherals and other crucial uses.  Thus, *despite not being a mapreduce mode*,
 zero-immediates cause multiple hits on the same element.
 
-Recall above that mapreduce mode is not actually mapreduce at all: it is
+Mapreduce mode is not actually mapreduce at all: it is
 a relaxation of the normal rule where if the destination is a Scalar the
 Vector for-looping is not terminated on first write to the destination.
 Instead, the developer is expected to exploit the strict Program Order,