From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 4 Apr 2018 20:00:29 +0000 (-0700)
Subject: Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instructions... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;ds=sidebyside;h=4856220f05094a870e9544523428b85ec597fd42;p=riscv-isa-sim.git

Revert "Fix for issue #183: No illegal instruction exception for c.sxxi instructions encoded with zero shift amount"

This reverts commit be0555d585b332fd0496affe559c0a5a4e7e5644.

See #190
---

diff --git a/riscv/insns/c_slli.h b/riscv/insns/c_slli.h
index 19d7908..24fbb13 100644
--- a/riscv/insns/c_slli.h
+++ b/riscv/insns/c_slli.h
@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_zimm() < xlen && insn.rvc_zimm() > 0);
+require(insn.rvc_zimm() < xlen);
 WRITE_RD(sext_xlen(RVC_RS1 << insn.rvc_zimm()));
diff --git a/riscv/insns/c_srai.h b/riscv/insns/c_srai.h
index 7b594e9..f6638b1 100644
--- a/riscv/insns/c_srai.h
+++ b/riscv/insns/c_srai.h
@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_zimm() < xlen && insn.rvc_zimm() > 0);
+require(insn.rvc_zimm() < xlen);
 WRITE_RVC_RS1S(sext_xlen(sext_xlen(RVC_RS1S) >> insn.rvc_zimm()));
diff --git a/riscv/insns/c_srli.h b/riscv/insns/c_srli.h
index 008ae62..f410fef 100644
--- a/riscv/insns/c_srli.h
+++ b/riscv/insns/c_srli.h
@@ -1,3 +1,3 @@
 require_extension('C');
-require(insn.rvc_zimm() < xlen && insn.rvc_zimm() > 0);
+require(insn.rvc_zimm() < xlen);
 WRITE_RVC_RS1S(sext_xlen(zext_xlen(RVC_RS1S) >> insn.rvc_zimm()));