From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 27 Feb 2022 18:48:28 +0000 (+0000)
Subject: whoops ALU common output target must be XLEN-bit,
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;ds=sidebyside;h=8d0c40fdf6335120e440a6bdba9aa0875239e843;p=soc.git

whoops ALU common output target must be XLEN-bit,
cannot set to length of output (o) using Signal.like
---

diff --git a/src/soc/fu/common_output_stage.py b/src/soc/fu/common_output_stage.py
index c4f085fd..a79179bc 100644
--- a/src/soc/fu/common_output_stage.py
+++ b/src/soc/fu/common_output_stage.py
@@ -11,6 +11,7 @@ class CommonOutputStage(PipeModBase):
         super().__init__(pspec, "output")
 
     def elaborate(self, platform):
+        XLEN = self.pspec.XLEN
         m = Module()
         comb = m.d.comb
         op = self.i.ctx.op
@@ -49,7 +50,7 @@ class CommonOutputStage(PipeModBase):
         # XXX ah.  right.  this needs to be done only if the *mode* is 32-bit
         # (an MSR bit)
         # see https://bugs.libre-soc.org/show_bug.cgi?id=424
-        target = Signal.like(o)
+        target = Signal(XLEN, reset_less=True)
         #with m.If(op.is_32bit):
         #    comb += target.eq(o[:32])
         #with m.Else():