From: Luke Kenneth Casson Leighton Date: Wed, 25 Jul 2018 08:18:51 +0000 (+0100) Subject: code-shuffle to use axi slave fast bus X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=02eb92231842a122625b8f3ab9d861cf90d5d0c1;p=pinmux.git code-shuffle to use axi slave fast bus --- diff --git a/src/bsv/peripheral_gen/base.py b/src/bsv/peripheral_gen/base.py index 4e17b4b..0ef4cd2 100644 --- a/src/bsv/peripheral_gen/base.py +++ b/src/bsv/peripheral_gen/base.py @@ -45,12 +45,16 @@ class PBase(object): " `define %(bend)s 'h%(end)08X // %(comment)s" % locals(), offs) - def axi_slave_name(self, name, ifacenum): + def axi_master_name(self, name, ifacenum): name = name.upper() - return "{0}{1}_slave_num".format(name, ifacenum) + return "{0}{1}_laster_num".format(name, ifacenum) - def axi_slave_idx(self, idx, name, ifacenum): - name = self.axi_slave_name(name, ifacenum) + def axi_slave_name(self, name, ifacenum, typ=''): + name = name.upper() + return "{0}{1}_{2}slave_num".format(name, ifacenum, typ) + + def axi_slave_idx(self, idx, name, ifacenum, typ): + name = self.axi_slave_name(name, ifacenum, typ) return ("typedef {0} {1};".format(idx, name), 1) def axi_addr_map(self, name, ifacenum): @@ -262,10 +266,10 @@ class PeripheralIface(object): return ('', 0) return self.slow.axi_reg_def(start, self.ifacename, count) - def axi_slave_idx(self, start, count): + def axi_slave_idx(self, start, count, typ): if not self.slow: return ('', 0) - return self.slow.axi_slave_idx(start, self.ifacename, count) + return self.slow.axi_slave_idx(start, self.ifacename, count, typ) def axi_addr_map(self, count): if not self.slow: @@ -333,13 +337,13 @@ class PeripheralInterfaces(object): start += offs return '\n'.join(list(filter(None, ret))) - def _axi_num_idx(self, start, template, typ, getfn, *args): + def _axi_num_idx(self, start, template, typ, idxtype, *args): ret = [] for (name, count) in self.ifacecount: for i in range(count): if self.is_on_fastbus(name, i): continue - (rdef, offs) = getattr(self.data[name], getfn)(start, i) + (rdef, offs) = self.data[name].axi_slave_idx(start, i, idxtype) #print ("ifc", name, rdef, offs) ret.append(rdef) start += offs @@ -349,7 +353,11 @@ class PeripheralInterfaces(object): def axi_slave_idx(self, *args): return self._axi_num_idx(0, axi_slave_declarations, 'slave', - 'axi_slave_idx', *args) + '', *args) + + def axi_fastslave_idx(self, *args): + return self._axi_num_idx(0, axi_fastslave_declarations, 'fastslave', + 'fast', *args) def axi_addr_map(self, *args): ret = [] diff --git a/src/bsv/peripheral_gen/eint.py b/src/bsv/peripheral_gen/eint.py index 825f3eb..e67aa8e 100644 --- a/src/bsv/peripheral_gen/eint.py +++ b/src/bsv/peripheral_gen/eint.py @@ -14,7 +14,7 @@ class eint(PBase): def axi_slave_name(self, name, ifacenum): return '' - def axi_slave_idx(self, idx, name, ifacenum): + def axi_slave_idx(self, idx, name, ifacenum, typ): return ('', 0) def axi_addr_map(self, name, ifacenum): diff --git a/src/bsv/peripheral_gen/gpio.py b/src/bsv/peripheral_gen/gpio.py index 418454b..90671a5 100644 --- a/src/bsv/peripheral_gen/gpio.py +++ b/src/bsv/peripheral_gen/gpio.py @@ -16,7 +16,7 @@ class gpio(PBase): def num_axi_regs32(self): return 2 - def axi_slave_idx(self, idx, name, ifacenum): + def axi_slave_idx(self, idx, name, ifacenum, typ): """ generates AXI slave number definition, except GPIO also has a muxer per bank """ @@ -24,8 +24,8 @@ class gpio(PBase): mname = 'mux' + name[4:] mname = mname.upper() print "AXIslavenum", name, mname - (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum) - (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum) + (ret, x) = PBase.axi_slave_idx(self, idx, name, ifacenum, typ) + (ret2, x) = PBase.axi_slave_idx(self, idx + 1, mname, ifacenum, typ) return ("%s\n%s" % (ret, ret2), 2) def mkslow_peripheral(self, size=0): diff --git a/src/bsv/peripheral_gen/jtag.py b/src/bsv/peripheral_gen/jtag.py index 3ccf6ad..45025c6 100644 --- a/src/bsv/peripheral_gen/jtag.py +++ b/src/bsv/peripheral_gen/jtag.py @@ -17,10 +17,10 @@ class jtag(PBase): jtag{0}.scan_out_5_i(1'b0); endrule """ - def axi_slave_name(self, name, ifacenum): + def axi_slave_name(self, name, ifacenum, typ=''): return '' - def axi_slave_idx(self, idx, name, ifacenum): + def axi_slave_idx(self, idx, name, ifacenum, typ): return ('', 0) def axi_addr_map(self, name, ifacenum):