From: Luke Kenneth Casson Leighton Date: Sun, 27 May 2018 15:22:35 +0000 (+0100) Subject: add scalar detection diagram X-Git-Tag: convert-csv-opcode-to-binary~5331 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=06ce55c6348e990828ff91505aace94b289325cd;p=libreriscv.git add scalar detection diagram --- diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn index 4af851578..c884bb956 100644 --- a/simple_v_extension.mdwn +++ b/simple_v_extension.mdwn @@ -1778,7 +1778,7 @@ discussion then led to the question of OoO architectures > relevant, is that the imprecise model increases the size of the context > structure, as the microarchitectural guts have to be spilled to memory.) ------ +## Zero/Non-zero Predication >> >  it just occurred to me that there's another reason why the data >> > should be left instead of zeroed.  if the standard register file is @@ -1808,9 +1808,19 @@ discussion then led to the question of OoO architectures > there may be a way to implement DTM as well. ------- +## Implementation detail for scalar-only op detection -* implementation detail for scalar-only op detection +Note: this is just one possible implementation. Another implementation +may choose to treat *all* operations as vectorised (including treating +scalars as vectors of length 1), choosing to add an extra pipeline stage +dedicated to + +This section *specifically* covers the implementor's freedom to choose +that they wish to minimise disruption to an existing design by detecting +"scalar-only operations", bypassing the vectorisation phase (which may +or may not require an additional pipeline stage) + +[[scalardetect.png]] >> For scalar ops an implementation may choose to compare 2-3 bits through an >> AND gate: are src & dest scalar? Yep, ok send straight to ALU  (or instr