From: lkcl Date: Sat, 15 Apr 2023 22:08:13 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls009_v1~62 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0a5777924bc4697f96edc93476764492a8d7255b;p=libreriscv.git --- diff --git a/openpower/sv/remap.mdwn b/openpower/sv/remap.mdwn index 9aa4c130c..c65f41b95 100644 --- a/openpower/sv/remap.mdwn +++ b/openpower/sv/remap.mdwn @@ -37,9 +37,12 @@ Vector ISAs which would typically only have a limited set of instructions that can be structure-packed (LD/ST typically), REMAP may be applied to literally any instruction: CRs, Arithmetic, Logical, LD/ST, anything. -Note that REMAP does not *directly* apply to sub-vector elements: that -is what swizzle is for. Swizzle *can* however be applied to the same -instruction as REMAP. As explained in [[sv/mv.swizzle]], [[sv/mv.vec]] and the [[svp64/appendix]], Pack and Unpack EXTRA Mode bits +When SUBVL is greater than 1 the group of Subvector +elements are kept together, effectively the group becomes the +element, and the group is REMAPed together. +Swizzle *can* however be applied to the same +instruction as REMAP, providing re-sequencing of +Subvector elements that REMAP cannot. Also as explained in [[sv/mv.swizzle]], [[sv/mv.vec]] and the [[svp64/appendix]], Pack and Unpack EXTRA Mode bits can extend down into Sub-vector elements to perform vec2/vec3/vec4 sequential reordering, but even here, REMAP is not extended down to the actual sub-vector elements themselves.