From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 24 Dec 2021 13:49:19 +0000 (+0000)
Subject: enable instruction redirect in mmu ifetch test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0aa2aee57a4b093b70d76a12c374962ad7d66503;p=soc.git

enable instruction redirect in mmu ifetch test
---

diff --git a/src/soc/simple/test/test_issuer_mmu_ifetch.py b/src/soc/simple/test/test_issuer_mmu_ifetch.py
index 4d434c7f..a5031a53 100644
--- a/src/soc/simple/test/test_issuer_mmu_ifetch.py
+++ b/src/soc/simple/test/test_issuer_mmu_ifetch.py
@@ -39,7 +39,7 @@ from soc.experiment.test import pagetables
 
 class MMUTestCase(TestAccumulatorBase):
 
-    def cse_virtual_ld_st(self):
+    def case_virtual_ld_st(self):
         lst = ["stb 10,0(2)",
                "addi 10,0, -4",
                "stb 10,0(5)",
@@ -60,7 +60,8 @@ class MMUTestCase(TestAccumulatorBase):
 
         # set virtual and non-privileged
         initial_msr = 1 << MSR.PR # must set "problem" state
-        initial_msr |= 1 << MSR.DR # set "virtual" state
+        initial_msr |= 1 << MSR.DR # set "virtual" state for data
+        initial_msr |= 1 << MSR.IR # set "virtual" state for instructions
 
         # set PRTBL to 0x1000000
         initial_sprs = {720: 0x1000000} # PRTBL
@@ -83,7 +84,8 @@ class MMUTestCase(TestAccumulatorBase):
 
         # set virtual and non-privileged
         initial_msr = 1 << MSR.PR # must set "problem" state
-        initial_msr |= 1 << MSR.DR # set "virtual" state
+        initial_msr |= 1 << MSR.DR # set "virtual" state for data
+        initial_msr |= 1 << MSR.IR # set "virtual" state for instructions
 
         print("MMUTEST: initial_msr=",initial_msr)
         self.add_case(Program(lst, bigendian), initial_regs,