From: Andrew Waterman Date: Sat, 15 Apr 2017 01:11:49 +0000 (-0700) Subject: Fix illegal-instruction test when S-mode is not implemented X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=0d53d12133bd3f7dce0e3731a5bc7dc0c1facc9d;p=riscv-tests.git Fix illegal-instruction test when S-mode is not implemented --- diff --git a/isa/rv64mi/illegal.S b/isa/rv64mi/illegal.S index 30105e6..a1b445f 100644 --- a/isa/rv64mi/illegal.S +++ b/isa/rv64mi/illegal.S @@ -21,6 +21,15 @@ bad2: .word 0 j fail + # Skip the rest of the test if S-mode is not present. + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 + csrr t2, mstatus + and t2, t2, t0 + bne t1, t2, pass + # Test vectored interrupts if they are supported. test_vectored_interrupts: csrwi mip, MIP_SSIP @@ -33,23 +42,18 @@ test_vectored_interrupts: csrsi mstatus, MSTATUS_MIE 1: j 1b - msip: csrw mtvec, s0 - # Skip the rest of the test if S-mode is not present. - li t0, MSTATUS_MPP - csrc mstatus, t0 - li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S - csrs mstatus, t1 - csrr t2, mstatus - and t2, t2, t0 - bne t1, t2, pass - # Delegate supervisor software interrupts so WFI won't stall. csrwi mideleg, MIP_SSIP + # Enter supervisor mode. la t0, 1f csrw mepc, t0 + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 mret 1: