From: Andrew Waterman Date: Fri, 24 Jan 2014 09:08:40 +0000 (-0800) Subject: Handle CSR permissions correctly X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=127fdd1d949715e32053fca5a4212dcb09790d2d;p=riscv-isa-sim.git Handle CSR permissions correctly --- diff --git a/riscv/decode.h b/riscv/decode.h index 4abd9f9..ceaf492 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -169,11 +169,12 @@ private: } while(0) #define validate_csr(which, write) ({ \ - int write_priv = ((which) >> 10) & 3; \ - int read_priv = ((which) >> 8) & 3; \ - if ((which) == CSR_FCSR || (which) == CSR_FFLAGS || (which) == CSR_FRM) \ - require_fp; \ - if (read_priv > 0 || (write_priv > 0 && (write))) require_supervisor; \ + unsigned my_priv = (p->get_state()->sr & SR_S) ? 1 : 0; \ + unsigned read_priv = ((which) >> 10) & 3; \ + unsigned write_priv = (((which) >> 8) & 3); \ + if (read_priv == 3) read_priv = write_priv, write_priv = -1; \ + if (my_priv < ((write) ? write_priv : read_priv)) \ + throw trap_privileged_instruction(); \ (which); }) #endif diff --git a/riscv/processor.cc b/riscv/processor.cc index 067288c..05fee79 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -318,6 +318,9 @@ reg_t processor_t::get_pcr(int which) return state.cause; case CSR_PTBR: return state.ptbr; + case CSR_SEND_IPI: + case CSR_CLEAR_IPI: + return 0; case CSR_ASID: return 0; case CSR_FATC: @@ -338,7 +341,7 @@ reg_t processor_t::get_pcr(int which) sim->get_htif()->tick(); // not necessary, but faster return state.fromhost; default: - return -1; + throw trap_illegal_instruction(); } }