From: Albert Ou <albert@sifive.com>
Date: Fri, 5 Jan 2018 03:51:24 +0000 (-0800)
Subject: uart: Eliminate systemic baud rate error with low divisor values
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=14ffd35f5c14771375e0a28c415abe6ba5db92e1;hp=14ffd35f5c14771375e0a28c415abe6ba5db92e1;p=sifive-blocks.git

uart: Eliminate systemic baud rate error with low divisor values

This refactors the receiver logic to compensate for the case of the baud
rate divisor not being multiple of the oversampling period.

Previously, the bit time was effectively rounded to (s * floor(div / s))
cycles, where "s" is the oversampling factor - the number of
intermediate samples for each data bit.  The remainder r = (div % s) was
ignored, thereby resulting in gradually accumulated drift that became
significant for divisor values on the same order of magnitude as "s".

The revised approach inserts the required additional delay by extending
the last "r" samples of a given data bit by one cycle each.
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