From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 23 Jul 2019 15:36:11 +0000 (+0100)
Subject: add fpsqrt experiment
X-Git-Tag: ls180-24jan2020~753
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=15ea1d39ca80123c0e524160766fa069150da831;p=ieee754fpu.git

add fpsqrt experiment
---

diff --git a/src/ieee754/fpdiv/div0.py b/src/ieee754/fpdiv/div0.py
index 34d7529f..16a78c6e 100644
--- a/src/ieee754/fpdiv/div0.py
+++ b/src/ieee754/fpdiv/div0.py
@@ -81,21 +81,38 @@ class FPDivStage0Mod(Elaboratable):
             # result is therefore 0.4999999 (0.5/0.99999) and 1.9999998
             # (0.99999/0.5).
 
-            # zero-extend the mantissas (room for sticky/round/guard)
-            # plus the extra MSB.
-            am0 = Signal(len(self.i.a.m)+3, reset_less=True)
-            bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
-            m.d.comb += [
-                         am0.eq(Cat(0,0,0,self.i.a.m, 0)),
-                         bm0.eq(Cat(0,0,0,self.i.b.m, 0)),
-                        ]
-
-            m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
-                         self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
-                         self.o.dividend[len(self.i.a.m)+extra:].eq(am0),
-                         self.o.divisor_radicand.eq(bm0),
-                         self.o.operation.eq(Const(0)) # XXX DIV operation
-                ]
+            # DIV
+            with m.If(self.i.ctx.op == 0):
+                am0 = Signal(len(self.i.a.m)+3, reset_less=True)
+                bm0 = Signal(len(self.i.b.m)+3, reset_less=True)
+                m.d.comb += [
+                             am0.eq(Cat(0,0,0,self.i.a.m, 0)),
+                             bm0.eq(Cat(0,0,0,self.i.b.m, 0)),
+                            ]
+
+                # zero-extend the mantissas (room for sticky/round/guard)
+                # plus the extra MSB.
+                m.d.comb += [self.o.z.e.eq(self.i.a.e - self.i.b.e + 1),
+                             self.o.z.s.eq(self.i.a.s ^ self.i.b.s),
+                             self.o.dividend[len(self.i.a.m)+extra:].eq(am0),
+                             self.o.divisor_radicand.eq(bm0),
+                             self.o.operation.eq(Const(0)) # XXX DIV operation
+                    ]
+
+            # SQRT
+            with m.Elif(self.i.ctx.op == 1):
+                am0 = Signal(len(self.i.a.m)+3, reset_less=True)
+                with m.If(self.i.a.e[0]):
+                    m.d.comb += am0.eq(Cat(0,0, self.i.a.m, 0))
+                    m.d.comb += self.o.z.e.eq(((self.i.a.e+1) >> 1))
+                with m.Else():
+                    m.d.comb += am0.eq(Cat(0, 0, 0, self.i.a.m))
+                    m.d.comb += self.o.z.e.eq((self.i.a.e >> 1))
+
+                m.d.comb += [self.o.z.s.eq(self.i.a.s),
+                             self.o.divisor_radicand.eq(am0),
+                             self.o.operation.eq(Const(1)) # XXX SQRT operation
+                    ]
 
         # these are required and must not be touched
         m.d.comb += self.o.oz.eq(self.i.oz)