From: Wesley W. Terpstra <wesley@sifive.com>
Date: Mon, 8 May 2017 08:08:37 +0000 (-0700)
Subject: xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=178ac84b59ebab63c182b821857f2b217cbbf17f;hp=9cb80ac9134ad4036e2ae40fb9be8f0f3e7065a4;p=sifive-blocks.git

xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12)
---

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
index 2e376d0..ae7cca5 100644
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
@@ -38,18 +38,16 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
   axi_to_pcie_x1.control :=
     AXI4Buffer()(
     AXI4UserYanker()(
-    AXI4Fragmenter()(
-    AXI4IdIndexer(idBits=0)(
     TLToAXI4(beatBytes=4)(
-    control)))))
+    TLFragmenter(4, p(coreplex.CacheBlockBytes))(
+    control))))
 
   master :=
     TLWidthWidget(8)(
     AXI4ToTL()(
     AXI4UserYanker(capMaxFlight=Some(8))(
     AXI4Fragmenter()(
-    AXI4IdIndexer(idBits=0)(
-    axi_to_pcie_x1.master)))))
+    axi_to_pcie_x1.master))))
 
   intnode := axi_to_pcie_x1.intnode
 
diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
index d9ffe8b..fa4b31b 100644
--- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
+++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala
@@ -205,7 +205,8 @@ class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule
       address       = List(AddressSet(0x50000000L, 0x03ffffffL)),
       resources     = device.reg,
       supportsWrite = TransferSizes(1, 4),
-      supportsRead  = TransferSizes(1, 4))),
+      supportsRead  = TransferSizes(1, 4),
+      interleavedId = Some(0))), // AXI4-Lite never interleaves responses
     beatBytes = 4)))
 
   val master = AXI4MasterNode(Seq(AXI4MasterPortParameters(