From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 3 Jun 2018 21:39:05 +0000 (+0100)
Subject: update
X-Git-Tag: convert-csv-opcode-to-binary~5304
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1b94c4a742f85bf226fe2b01ea17b4c6d21b52d2;p=libreriscv.git

update
---

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index b2e3c92c0..22142259f 100644
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -318,6 +318,7 @@ for (int i = 0; i < VL; ++i)
 
  \begin{itemize}
    \item Same register(s) can have multiple "interpretations"
+   \item Set "real" register (scalar) without needing to set/unset CSRs.
    \item xBitManip plus SIMD plus xBitManip = Hi/Lo bitops
    \item (32-bit GREV plus 4x8-bit SIMD plus 32-bit GREV:\\
 	     GREV @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
@@ -325,7 +326,7 @@ for (int i = 0; i < VL; ++i)
 	     (BEXT/BDEP @ VL=N,wid=32; SIMD @ VL=Nx4,wid=8)
    \item Same register(s) can be offset (no need for VSLIDE)\vspace{6pt}
   \end{itemize}
-  Note:\vspace{10pt}
+  Note:
    \begin{itemize}
    \item xBitManip reduces O($N^{6}$) SIMD down to O($N^{3}$)
    \item Hi-Performance: Macro-op fusion (more pipeline stages?)