From: Luke Kenneth Casson Leighton Date: Tue, 9 Oct 2018 18:33:53 +0000 (+0100) Subject: get predicated-vectorised branch working X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1cc9962a861f9634db1d29ddd9628fef5f139098;p=riscv-isa-sim.git get predicated-vectorised branch working --- diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc index 7a67f6c..f579646 100644 --- a/riscv/insn_template_sv.cc +++ b/riscv/insn_template_sv.cc @@ -59,8 +59,10 @@ #define xstr(s) str(s) #define str(s) #s +#include "sv.h" + #ifdef INSN_TYPE_BRANCH - #define set_pc(x) insn.setpc(xlen, vlen, npc, x, *dest_offs, target_pred); + #define set_pc(x) insn.setpc(xlen, vlen, npc, x, *dest_offs, target_reg); #else #define set_pc _set_pc #endif @@ -99,6 +101,11 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) bool zeroingtarg = false; #endif sv_insn_t insn(p, bits, floatintmap, PRED_ARGS, OFFS_ARGS); +#ifdef INSN_TYPE_BRANCH + sv_pred_entry *r = insn.get_predentry(s_insn.rs2(), true); + reg_t _target_reg = 0; + reg_t *target_reg = NULL; +#endif reg_t sp = 0; if (vlen > 0) { @@ -114,7 +121,14 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) #endif #ifdef INSN_TYPE_BRANCH // all branch ops are rs1, rs2. take target (dest) predicate from rs2. - target_pred = insn.predicate(s_insn.rs2(), true, zeroingtarg); + if (r->active) + { + _target_reg = r->regidx; + target_reg = &_target_reg; + insn.predicate(s_insn.rs2(), true, zeroingtarg); + fprintf(stderr, "branch pred reg %ld pred %lx\n", + _target_reg, target_pred); + } #endif #ifdef INSN_CATEGORY_TWINPREDICATION #ifdef INSN_TYPE_C_STACK_LD @@ -246,6 +260,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc) if (insn.get_if_one_reg_vectorised() && (insn.get_saved_branch_rd() & mask) == (target_pred & mask)) { + fprintf(stderr, "vector branch ACTIVE\n"); _set_pc(insn.get_saved_branch_addr()); } #endif diff --git a/riscv/sv.cc b/riscv/sv.cc index c06bdd5..ba4fd53 100644 --- a/riscv/sv.cc +++ b/riscv/sv.cc @@ -191,9 +191,8 @@ uint64_t sv_insn_t::_rvc_spoffs_imm(uint64_t elwidth, uint64_t offs) } // for use in predicated branches. sets bit N if val=true; clears bit N if false -uint64_t sv_insn_t::rd_bitset(uint64_t bit, bool set) +uint64_t sv_insn_t::rd_bitset(reg_t reg, uint64_t bit, bool set) { - reg_t reg = rd(); uint64_t val = READ_REG(reg); if (set) { val |= (1<