From: lkcl Date: Wed, 29 Jun 2022 17:13:58 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~1461 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1efda2962cfd1cc1f916b3fce76de71b529a10ca;p=libreriscv.git --- diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index 2fd44b865..89ead3407 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -277,7 +277,9 @@ Vector instructions in RISC-V as there are in the RV64GC Scalar base. The question then becomes: with all the duplication of arithmetic operations just to make the registers scalar or vector, why not leverage the *existing* Scalar ISA with some sort of "context" -or prefix that augments its behaviour? Make "Scalar instruction" +or prefix that augments its behaviour? Separate out the +"looping" from "thing being looped on" (the elements), +make "Scalar instruction" synonymous with "Vector Element instruction" and through nothing more than contextual augmentation the Scalar ISA *becomes* the Vector ISA. @@ -286,8 +288,11 @@ the Instruction Decode phase is greatly simplified, reducing design complexity and leaving plenty of headroom for further expansion. +[[!img "svp64-primer/img/power_pipelines.svg" ]] + Remarkably this is not a new idea. Intel's x86 `REP` instruction -gives the base concept, but in 1994 it was Peter Hsu, the designer +gives the base concept, and the Z80 had something similar. +But in 1994 it was Peter Hsu, the designer of the MIPS R8000, who first came up with the idea of Vector-augmented prefixing of an existing Scalar ISA. Relying on a multi-issue Out-of-Order Execution Engine, the prefix would mark which of the registers were to be treated as @@ -298,7 +303,8 @@ jammed multiple scalar operations into the Multi-Issue Execution Engine. The only reason that the team did not take this forward into a commercial product was because they could not work out how to cleanly do OoO -multi-issue at the time. +multi-issue at the time (leveraging Multi-Issue is the most logical +way to exploit the Vector-Prefix concept) In its simplest form, then, this "prefixing" idea is a matter of: