From: Cesar Strauss Date: Sun, 6 Dec 2020 11:34:35 +0000 (-0300) Subject: Update GTKWave documents to work with latest cxxsim X-Git-Tag: 24jan2021_ls180~72 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=1f5069f0480c08a4c03838214f9fdc8aef94bac9;p=soc.git Update GTKWave documents to work with latest cxxsim * Hierarchy begins at "top", just like pysim * Avoid intermediate signals, that work differently on both * Use the new "submodule" style in write_gtkw --- diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py index 1198d416..d0bf87fb 100644 --- a/src/soc/experiment/alu_fsm.py +++ b/src/soc/experiment/alu_fsm.py @@ -25,8 +25,7 @@ from nmutil.iocontrol import PrevControl, NextControl from soc.fu.base_input_record import CompOpSubsetBase from nmutil.gtkw import write_gtkw -from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim, - nmigen_sim_top_module) +from nmutil.sim_tmp_alternative import (Simulator, is_engine_pysim) class CompFSMOpSubset(CompOpSubsetBase): @@ -225,25 +224,22 @@ def test_shifter(): ('op__sdir', 'in'), ('p_data_i[7:0]', 'in'), ('p_shift_i[7:0]', 'in'), - ('p_valid_i', 'in'), - ('p_ready_o' if is_engine_pysim() else 'p_p_ready_o', 'out'), - ]), + ({'submodule': 'p'}, [ + ('p_valid_i', 'in'), + ('p_ready_o', 'out')])]), ('internal', [ 'fsm_state' if is_engine_pysim() else 'fsm_state[1:0]', 'count[3:0]', - 'shift_reg[7:0]', - ]), + 'shift_reg[7:0]']), ('next port', [ ('n_data_o[7:0]', 'out'), - ('n_valid_o' if is_engine_pysim() else 'n_n_valid_o', 'out'), - ('n_ready_i', 'in'), - ]), - ] + ({'submodule': 'n'}, [ + ('n_valid_o', 'out'), + ('n_ready_i', 'in')])])] - module = nmigen_sim_top_module + "shf" write_gtkw("test_shifter.gtkw", "test_shifter.vcd", gtkwave_desc, gtkwave_style, - module=module, loc=__file__, base='dec') + module='top.shf', loc=__file__, base='dec') sim = Simulator(m) sim.add_clock(1e-6) diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index fb9fbb28..7120901b 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -391,7 +391,6 @@ def scoreboard_sim(op): def test_compunit_fsm(): - top = "top.cu" if is_engine_pysim() else "cu" style = { 'in': {'color': 'orange'}, 'out': {'color': 'yellow'}, @@ -412,13 +411,15 @@ def test_compunit_fsm(): 'src2_i[7:0]']), ('result port', 'out', [ 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']), - ('alu', {'module': top+'.alu'}, [ + ('alu', {'submodule': 'alu'}, [ ('prev port', 'in', [ 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]', - 'p_valid_i', 'p_ready_o']), + ({'submodule': 'p'}, + ['p_valid_i', 'p_ready_o'])]), ('next port', 'out', [ - 'n_data_o[7:0]', 'n_valid_o', 'n_ready_i']), - ]), + 'n_data_o[7:0]', + ({'submodule': 'n'}, + ['n_valid_o', 'n_ready_i'])])]), ('debug', {'module': 'top'}, ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])] @@ -426,7 +427,7 @@ def test_compunit_fsm(): "test_compunit_fsm1.gtkw", "test_compunit_fsm1.vcd", traces, style, - module=top + module='top.cu' ) m = Module() alu = Shifter(8) @@ -746,7 +747,7 @@ def test_compunit_regspec3(): 'src1_i[15:0]']), ('result port', 'out', [ 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']), - ('alu', {'module': 'top.cu.alu'}, [ + ('alu', {'submodule': 'alu'}, [ ('prev port', 'in', [ 'oper_i_None__insn_type', 'i1[15:0]', 'valid_i', 'ready_o']), @@ -808,7 +809,7 @@ def test_compunit_regspec1(): 'src2_i[15:0]']), ('result port', 'out', [ 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']), - ('alu', {'module': 'top.cu.alu'}, [ + ('alu', {'submodule': 'alu'}, [ ('prev port', 'in', [ 'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]', 'valid_i', 'ready_o']), diff --git a/src/soc/fu/compunits/formal/proof_fu.py b/src/soc/fu/compunits/formal/proof_fu.py index e55b640b..c45e8fe4 100644 --- a/src/soc/fu/compunits/formal/proof_fu.py +++ b/src/soc/fu/compunits/formal/proof_fu.py @@ -214,7 +214,7 @@ class FUTestCase(FHDLTestCase): 'src1_i[15:0]']), ('result port', 'out', [ 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']), - ('alu', {'module': 'top.dut.alu'}, [ + ('alu', {'submodule': 'alu'}, [ ('prev port', 'in', [ 'oper_i_None__insn_type', 'i1[15:0]', 'valid_i', 'ready_o']),