From: Luke Kenneth Casson Leighton Date: Mon, 31 Jan 2022 15:29:44 +0000 (+0000) Subject: use an SRLatch for cache_valids, at least it reduces graphviz size X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=205af15112e2dcd44b6f1d29ef032b528666a18d;p=soc.git use an SRLatch for cache_valids, at least it reduces graphviz size --- diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py index d24706ed..12651583 100644 --- a/src/soc/experiment/icache.py +++ b/src/soc/experiment/icache.py @@ -34,6 +34,7 @@ from nmutil.iocontrol import RecordObject from nmigen.utils import log2_int from nmigen.lib.coding import Decoder from nmutil.util import Display +from nmutil.latch import SRLatch #from nmutil.plru import PLRU from soc.experiment.plru import PLRU, PLRUs @@ -509,7 +510,7 @@ class ICache(FetchUnitInterface, Elaboratable): ctag = Signal(TAG_RAM_WIDTH) comb += rd_tag.addr.eq(req_index) comb += ctag.eq(rd_tag.data) - comb += cvb.eq(cache_valids.word_select(req_index, NUM_WAYS)) + comb += cvb.eq(cache_valids.q.word_select(req_index, NUM_WAYS)) m.submodules.store_way_e = se = Decoder(NUM_WAYS) comb += se.i.eq(r.store_way) comb += se.n.eq(~i_in.req) @@ -648,7 +649,7 @@ class ICache(FetchUnitInterface, Elaboratable): # Force misses on that way while reloading that line idx = req_index*NUM_WAYS + replace_way # 2D index, 1st dim: NUM_WAYS - sync += cache_valids.bit_select(idx, 1).eq(0) + comb += cache_valids.r.eq(1<