From: Luke Kenneth Casson Leighton Date: Thu, 11 Mar 2021 18:29:26 +0000 (+0000) Subject: whoops sort out when svstate not active in ISACaller X-Git-Tag: convert-csv-opcode-to-binary~61 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2133c0f5cf4d2cd4adc15e5f7fd58e1877c8b7be;p=soc.git whoops sort out when svstate not active in ISACaller --- diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 26a10d09..f7a015ad 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -652,7 +652,8 @@ class ISACaller: yield self.dec2.dec.bigendian.eq(self.bigendian) yield self.dec2.state.msr.eq(self.msr.value) yield self.dec2.state.pc.eq(pc) - yield self.dec2.state.svstate.eq(self.svstate.spr.value) + if self.svstate is not None: + yield self.dec2.state.svstate.eq(self.svstate.spr.value) # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set yield Settle() @@ -835,11 +836,6 @@ class ISACaller: dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {} print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname) - # get SVSTATE srcstep. TODO: dststep (twin predication) - srcstep = self.svstate.srcstep.asint(msb0=True) - vl = self.svstate.vl.asint(msb0=True) - mvl = self.svstate.maxvl.asint(msb0=True) - # VL=0 in SVP64 mode means "do nothing: skip instruction" if self.is_svp64_mode and vl == 0: self.pc.update(self.namespace, self.is_svp64_mode) @@ -856,10 +852,6 @@ class ISACaller: # doing this is not part of svp64, it's because output # registers, to be modified, need to be in the namespace. regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name) - # here's where we go "vector". TODO: zero-testing (RA_IS_ZERO) - # XXX already done by PowerDecoder2, now - #if is_vec: - # regnum += srcstep # TODO, elwidth overrides # in case getting the register number is needed, _RA, _RB regname = "_" + name