From: Luke Kenneth Casson Leighton Date: Fri, 2 Nov 2018 07:08:08 +0000 (+0000) Subject: add 32-bit FLW unit tests X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2c34cde67ab94f4681fcea2574f68af21fa82795;p=riscv-tests.git add 32-bit FLW unit tests --- diff --git a/isa/rv64uf/sv_fld_elwidth.S b/isa/rv64uf/sv_fld_elwidth.S index ee8a8e5..5590751 100644 --- a/isa/rv64uf/sv_fld_elwidth.S +++ b/isa/rv64uf/sv_fld_elwidth.S @@ -77,11 +77,11 @@ RVTEST_CODE_BEGIN # Start of test code. SV_ELWIDTH_TEST( fld , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata3, answer4) SV_ELWIDTH_TEST( fld , 6, 8, SV_W_32BIT, SV_W_16BIT, testdata4, answer5) + SV_ELWIDTH_TESTW(flw , 3, 4, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 ) + SV_ELWIDTH_TESTW(flw , 3, 4, SV_W_16BIT, SV_W_DFLT, testdata3, answer8) + SV_ELWIDTH_TESTW(flw , 5, 4, SV_W_16BIT, SV_W_32BIT, testdata3, answer4) /* - SV_ELWIDTH_TESTW(flw , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1, answer1 ) - SV_ELWIDTH_TESTW(flw , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata3, answer3) - SV_ELWIDTH_TESTW(flw , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata3, answer4) - SV_ELWIDTH_TESTW(flw , 6, 8, SV_W_32BIT, SV_W_16BIT, testdata4, answer5) + SV_ELWIDTH_TESTW(flw , 2, 4, SV_W_32BIT, SV_W_16BIT, testdata4, answer5) SV_ELWIDTH_TESTW(flw , 6, 8, SV_W_DFLT, SV_W_16BIT, testdata6, answer5) SV_ELWIDTH_TEST( ld , 5, 8, SV_W_32BIT, SV_W_16BIT, testdata1, @@ -188,6 +188,21 @@ testdata6: .dword 0x0 .dword 0x0 +answer7: + .dword 0xa5a5a5a549392919 + .dword 0xa5a5a5a589796959 + .dword 0x8777675747372717 + .dword 0xa5a5a5a5a5a5a5a5 + + .align 3 + +answer8: + + .float 42.0 + .float 44.0 + .float 1.0 + + .align 3 # Output data section. RVTEST_DATA_BEGIN # Start of test output data region. .align 3