From: Cesar Strauss Date: Fri, 1 Jan 2021 20:38:57 +0000 (-0300) Subject: Make all ports the same size, on the test ALU X-Git-Tag: 24jan2021_ls180~41 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2d731038ee10f5283cd909717ae5076276a63d6c;p=soc.git Make all ports the same size, on the test ALU The old regspec API can't cope with different port sizes. The CR port is now changed from 3 to "width" bits (16). The problem was that cr.ok went into the fourth bit, messing with the results. --- diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py index a780dd86..76d8e221 100644 --- a/src/soc/experiment/alu_hier.py +++ b/src/soc/experiment/alu_hier.py @@ -198,7 +198,7 @@ class ALU(Elaboratable): self.a, self.b = i[0], i[1] out = [] out.append(Data(width, name="alu_o")) - out.append(Data(3, name="alu_cr")) + out.append(Data(width, name="alu_cr")) self.out = Array(out) self.o = self.out[0] self.cr = self.out[1] diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py index f6635c32..ae4f8199 100644 --- a/src/soc/experiment/test/test_compalu_multi.py +++ b/src/soc/experiment/test/test_compalu_multi.py @@ -724,7 +724,7 @@ def test_compunit_regspec1(): inspec = [('INT', 'a', '0:15'), ('INT', 'b', '0:15')] outspec = [('INT', 'o', '0:15'), - ('INT', 'cr', '0:2')] + ('INT', 'cr', '0:15')] regspec = (inspec, outspec)