From: Michael Nolan Date: Mon, 9 Mar 2020 15:00:55 +0000 (-0400) Subject: Fix logical loop in DecodeA X-Git-Tag: div_pipeline~1742 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=2dc4be2d07a25cf0615334d6bc36599285b3880c;p=soc.git Fix logical loop in DecodeA --- diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 81805a73..436005c6 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -34,13 +34,13 @@ class DecodeA(Elaboratable): # select Register A field with m.If((self.sel_in == In1Sel.RA) | ((self.sel_in == In1Sel.RA_OR_ZERO) & - (self.reg_out.data != Const(0, 5)))): + (self.dec.RA[0:-1] != Const(0, 5)))): comb += self.reg_out.data.eq(self.dec.RA[0:-1]) comb += self.reg_out.ok.eq(1) # zero immediate requested with m.If((self.sel_in == In1Sel.RA_OR_ZERO) & - (self.reg_out.data == Const(0, 5))): + (self.reg_out.data == Const(0, 5))): comb += self.immz_out.eq(1) # decode SPR1 based on instruction type