From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 15 Jul 2020 13:13:28 +0000 (+0100)
Subject: select RA based on LDSTMode.update in PowerDecode2
X-Git-Tag: div_pipeline~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=31e910b9234f84bb4fd847657e52a724611961d6;p=soc.git

select RA based on LDSTMode.update in PowerDecode2
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 85a8c089..06bdf14e 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -18,7 +18,7 @@ from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
                                      CRInSel, CROutSel,
                                      LdstLen, In1Sel, In2Sel, In3Sel,
-                                     OutSel, SPR, RC)
+                                     OutSel, SPR, RC, LDSTMode)
 from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
 from soc.consts import MSR
 
@@ -361,7 +361,7 @@ class DecodeOut2(Elaboratable):
         comb = m.d.comb
 
         # update mode LD/ST uses read-reg A also as an output
-        with m.If(self.dec.op.upd):
+        with m.If(self.dec.op.upd == LDSTMode.update):
             comb += self.reg_out.eq(self.dec.RA)
             comb += self.reg_out.ok.eq(1)