From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 17 Jan 2020 14:14:18 +0000 (+0000)
Subject: update to new revision nmigen
X-Git-Tag: div_pipeline~1821
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=340e127f0ab73ae6753ee798aa2c39f7ca395599;p=soc.git

update to new revision nmigen
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index b3d1763c..209bc99c 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -1,5 +1,6 @@
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
+from nmigen.hdl.ast import unsigned
 from nmigen import Module, Const, Signal, Array, Cat, Elaboratable, Memory
 
 from regfile.regfile import RegFileArray, treereduce
@@ -421,9 +422,9 @@ class Scoreboard(Elaboratable):
         self.ls_imm_i = Signal(rwid, reset_less=True)
 
         # inputs
-        self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
-        self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
-        self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
+        self.int_dest_i = Signal(range(n_regs), reset_less=True) # Dest R# in
+        self.int_src1_i = Signal(range(n_regs), reset_less=True) # oper1 R# in
+        self.int_src2_i = Signal(range(n_regs), reset_less=True) # oper2 R# in
         self.reg_enable_i = Signal(reset_less=True) # enable reg decode
 
         # outputs
@@ -742,7 +743,7 @@ class IssueToScoreboard(Elaboratable):
         self.opw = opwid
         self.n_regs = n_regs
 
-        mqbits = (int(log(qlen) / log(2))+2, False)
+        mqbits = unsigned(int(log(qlen) / log(2))+2)
         self.p_add_i = Signal(mqbits) # instructions to add (from data_i)
         self.p_ready_o = Signal() # instructions were added
         self.data_i = Instruction.nq(n_in, "data_i", rwid, opwid)
diff --git a/src/scoreboard/addr_match.py b/src/scoreboard/addr_match.py
index 9d8e08e4..e42bbe52 100644
--- a/src/scoreboard/addr_match.py
+++ b/src/scoreboard/addr_match.py
@@ -61,7 +61,8 @@ class PartialAddrMatch(Elaboratable):
         sync = m.d.sync
 
         m.submodules.l = l = SRLatch(llen=self.n_adr, sync=False)
-        addrs_r = Array(Signal(self.bitwid, "a_r") for i in range(self.n_adr))
+        addrs_r = Array(Signal(self.bitwid, name="a_r") \
+                                for i in range(self.n_adr))
 
         # latch set/reset
         comb += l.s.eq(self.addr_en_i)
diff --git a/src/scoreboard/issue_unit.py b/src/scoreboard/issue_unit.py
index fb7578d9..3ec2a31c 100644
--- a/src/scoreboard/issue_unit.py
+++ b/src/scoreboard/issue_unit.py
@@ -18,9 +18,9 @@ class RegDecode(Elaboratable):
 
         # inputs
         self.enable_i = Signal(reset_less=True) # enable decoders
-        self.dest_i = Signal(max=wid, reset_less=True) # Dest R# in
-        self.src1_i = Signal(max=wid, reset_less=True) # oper1 R# in
-        self.src2_i = Signal(max=wid, reset_less=True) # oper2 R# in
+        self.dest_i = Signal(range(wid), reset_less=True) # Dest R# in
+        self.src1_i = Signal(range(wid), reset_less=True) # oper1 R# in
+        self.src2_i = Signal(range(wid), reset_less=True) # oper2 R# in
 
         # outputs
         self.dest_o = Signal(wid, reset_less=True) # Dest unary out