From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 28 Jun 2019 05:32:11 +0000 (+0100)
Subject: add cookie-cut FPDIV
X-Git-Tag: ls180-24jan2020~975
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=344f353645209b2802efa1afbf30d8e56a5a54f0;p=ieee754fpu.git

add cookie-cut FPDIV
---

diff --git a/src/ieee754/fpdiv/divstages.py b/src/ieee754/fpdiv/divstages.py
new file mode 100644
index 00000000..8d7489c7
--- /dev/null
+++ b/src/ieee754/fpdiv/divstages.py
@@ -0,0 +1,52 @@
+# IEEE Floating Point Divider
+
+from nmigen import Module
+from nmigen.cli import main, verilog
+
+from nmutil.singlepipe import (StageChain, SimpleHandshake)
+
+from ieee754.fpcommon.fpbase import FPState
+from ieee754.fpcommon.denorm import FPSCData
+from ieee754.fpcommon.postcalc import FPAddStage1Data
+
+# TODO: write these
+from .div0 import FPDivStage0Mod
+from .div1 import FPDivStage1Mod
+
+
+class FPDivStages(FPState, SimpleHandshake):
+
+    def __init__(self, width, id_wid):
+        FPState.__init__(self, "align")
+        self.width = width
+        self.id_wid = id_wid
+        SimpleHandshake.__init__(self, self) # pipeline is its own stage
+        self.m1o = self.ospec()
+
+    def ispec(self):
+        return FPSCData(self.width, self.id_wid, False)
+
+    def ospec(self):
+        return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
+
+    def setup(self, m, i):
+        """ links module to inputs and outputs
+        """
+
+        # chain DivStage0 and DivStage1
+        m0mod = FPDivStage0Mod(self.width, self.id_wid)
+        m1mod = FPDivStage1Mod(self.width, self.id_wid)
+
+        chain = StageChain([m0mod, m1mod])
+        chain.setup(m, i)
+
+        self.o = m1mod.o
+
+    def process(self, i):
+        return self.o
+
+    def action(self, m):
+        m.d.sync += self.m1o.eq(self.process(None))
+        m.next = "normalise_1"
+
+