From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Jul 2019 19:39:49 +0000 (+0100)
Subject: FP16 DIV seems to be working
X-Git-Tag: ls180-24jan2020~764
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=393ae306f9de78d381639e4e8887a6edd3aa76ca;p=ieee754fpu.git

FP16 DIV seems to be working
---

diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index 24bc7824..d18438e8 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -168,9 +168,9 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
                 op1 = randint(0, (1<<width)-1)
                 op2 = randint(0, (1<<width)-1)
 
-                op2 = 0x4000
-                op1 = 0x3c00
-                op2 = 0x3e00
+                #op2 = 0x4000
+                #op1 = 0x3c50
+                #op2 = 0x3e00
                 vals.append((op1, op2,))
     return vals
 
diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 119db0f5..f9ad69e3 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -81,7 +81,7 @@ class FPDIVBasePipe(ControlBase):
         ControlBase.__init__(self)
 
         pipechain = []
-        max_n_comb_stages = 3  # TODO (depends on how many RS's we want)
+        max_n_comb_stages = 2  # TODO (depends on how many RS's we want)
         # to which the answer: "as few as possible"
         # is required.  too many ReservationStations
         # means "big problems".
@@ -90,6 +90,7 @@ class FPDIVBasePipe(ControlBase):
         # probably related to having to add 4 in FPDivMuxInOut
         radix = pspec.log2_radix
         n_stages = pspec.core_config.n_stages // max_n_comb_stages
+        print ("n_stages", pspec.core_config.n_stages, n_stages)
         stage_idx = 0
 
         for i in range(n_stages):
@@ -163,6 +164,7 @@ class FPDIVMuxInOut(ReservationStations):
         # then there is guard, round and sticky at the LSB end.
         # also: round up to nearest radix
         fmt.m_width = roundup(fmt.m_width + 5, log2_radix)
+        print ("width", fmt.m_width)
 
         cfg = DivPipeCoreConfig(fmt.m_width, fmt.fraction_width, log2_radix)