From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 6 Apr 2020 11:15:28 +0000 (+0100)
Subject: add individual field-detection where field spec is "d0,d1,d2"
X-Git-Tag: div_pipeline~1451
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3a40cddd16f77259c9f15edaa5aecb12f1a1324d;p=soc.git

add individual field-detection where field spec is "d0,d1,d2"
---

diff --git a/libreriscv b/libreriscv
index 9a4012b3..18043345 160000
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 9a4012b31563923b466ea4889ee8c8847527ff16
+Subproject commit 1804334535fcfbe92a0f8abf5fb5399963032cf1
diff --git a/src/soc/decoder/power_fields.py b/src/soc/decoder/power_fields.py
index 26b59d46..4e7bee09 100644
--- a/src/soc/decoder/power_fields.py
+++ b/src/soc/decoder/power_fields.py
@@ -208,9 +208,18 @@ class DecodeFields:
         res = {}
         for field in fields:
             f, spec = field.strip().split(" ")
+            ss = spec[1:-1].split(",")
+            fs = f.split(",")
+            if len(fs) > 1:
+                individualfields = []
+                for f0, s0 in zip(fs, ss):
+                    txt = "%s (%s)" % (f0, s0)
+                    individualfields.append(txt)
+                if len(fs) > 1:
+                  res.update(self.decode_instruction_fields(individualfields))
             d = self.bitkls(*self.bitargs)
             idx = 0
-            for s in spec[1:-1].split(","):
+            for s in ss:
                 s = s.split(':')
                 if len(s) == 1:
                     d[idx] = int(s[0])
@@ -233,3 +242,7 @@ if __name__ == '__main__':
     dec = DecodeFields()
     dec.create_specs()
     forms, instrs = dec.forms, dec.instrs
+    for form, fields in instrs.items():
+        print ("Form", form)
+        for field, bits in fields.items():
+            print ("\tfield", field, bits)