From: solomatnikov Date: Fri, 23 Feb 2018 20:09:18 +0000 (-0800) Subject: Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (#49) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3dee15277598e45d7ac9d435f0365989c6d00f7e;p=sifive-blocks.git Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (#49) --- diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala index be7ff4a..b3e2db5 100644 --- a/src/main/scala/devices/i2c/I2C.scala +++ b/src/main/scala/devices/i2c/I2C.scala @@ -202,7 +202,7 @@ trait HasI2CModuleContents extends MultiIOModule with HasRegMap { s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18) val bitState = Reg(init = s_bit_idle) - val arbLost = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState === s_bit_idle) && stopCond && !bitCmdStop)) + val arbLost = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState =/= s_bit_idle) && stopCond && !bitCmdStop)) // bit FSM when (arbLost) {