From: Andrew Waterman <aswaterman@gmail.com>
Date: Fri, 2 Jan 2015 23:09:04 +0000 (-0800)
Subject: Reduce dependences on auto-generated code
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=3fd738af16ef977f1aa507e2525bb4c16fff9026;p=riscv-isa-sim.git

Reduce dependences on auto-generated code

In particular, precompiled headers ideally won't depend on any.
---

diff --git a/Makefile.in b/Makefile.in
index dcecc23..5ae226f 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -190,7 +190,7 @@ $(2)_c_objs := $$(patsubst %.c, %.o, $$($(2)_c_srcs))
 $(2)_deps := $$(patsubst %.o, %.d, $$($(2)_objs))
 $(2)_c_deps := $$(patsubst %.o, %.d, $$($(2)_c_objs))
 $(2)_pch_deps := $$(patsubst %.h, %.d, $$($(2)_precompiled_hdrs))
-$$($(2)_pch) : %.h.gch : %.h $$($(2)_gen_hdrs)
+$$($(2)_pch) : %.h.gch : %.h
 	$(COMPILE) $$<
 # If using clang, don't depend (and thus don't build) precompiled headers
 $$($(2)_objs) : %.o : %.cc $$($(2)_gen_hdrs) $(if $(filter-out clang,$(CC)),$$($(2)_pch))
diff --git a/riscv/gen_icache b/riscv/gen_icache
index c581b55..7ec3c69 100755
--- a/riscv/gen_icache
+++ b/riscv/gen_icache
@@ -1,9 +1,7 @@
 #!/bin/sh
-echo \#define ICACHE_SIZE $1
 n=$(($1-1))
-echo \#define ICACHE_SWITCH \\
 for i in `seq 0 $n`
 do
-  echo case $i: ICACHE_ACCESS\($i\)\; \\
+  echo case $i: ICACHE_ACCESS\($i\)\;
 done
 echo
diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index 92cb6de..2e5de5b 100644
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -16,7 +16,7 @@ mmu_t::~mmu_t()
 
 void mmu_t::flush_icache()
 {
-  for (size_t i = 0; i < ICACHE_SIZE; i++)
+  for (size_t i = 0; i < ICACHE_ENTRIES; i++)
     icache[i].tag = -1;
 }
 
diff --git a/riscv/mmu.h b/riscv/mmu.h
index 778e5fa..08d41be 100644
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -4,7 +4,6 @@
 #define _RISCV_MMU_H
 
 #include "decode.h"
-#include "icache.h"
 #include "trap.h"
 #include "common.h"
 #include "config.h"
@@ -74,10 +73,12 @@ public:
   store_func(uint32)
   store_func(uint64)
 
+  static const reg_t ICACHE_ENTRIES = 1024;
+
   inline size_t icache_index(reg_t addr)
   {
     // for instruction sizes != 4, this hash still works but is suboptimal
-    return (addr / 4) % ICACHE_SIZE;
+    return (addr / 4) % ICACHE_ENTRIES;
   }
 
   // load instruction from memory at aligned address.
@@ -140,7 +141,7 @@ private:
   memtracer_list_t tracer;
 
   // implement an instruction cache for simulator performance
-  icache_entry_t icache[ICACHE_SIZE];
+  icache_entry_t icache[ICACHE_ENTRIES];
 
   // implement a TLB for simulator performance
   static const reg_t TLB_ENTRIES = 256;
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 08ec2b7..40cc7dd 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -7,7 +7,6 @@
 #include "sim.h"
 #include "htif.h"
 #include "disasm.h"
-#include "icache.h"
 #include <cinttypes>
 #include <cmath>
 #include <cstdlib>
@@ -206,12 +205,12 @@ void processor_t::step(size_t n)
         ic_entry++; \
         pc = execute_insn(this, pc, fetch); \
         instret++; \
-        if (idx < ICACHE_SIZE-1 && unlikely(ic_entry->tag != pc)) break; \
+        if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
+        if (unlikely(ic_entry->tag != pc)) break; \
       }
 
-      switch (idx)
-      {
-        ICACHE_SWITCH; // auto-generated into icache.h
+      switch (idx) {
+        #include "icache.h"
       }
     }
   }
diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 0d5869d..9e5aa9f 100644
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -47,8 +47,10 @@ riscv_gen_hdrs = \
 riscv_gen_srcs = \
 	$(addsuffix .cc, $(call get_insn_list,$(src_dir)/riscv/encoding.h))
 
-icache.h:
-	$(src_dir)/riscv/gen_icache 1024 > $@.tmp
+icache_entries := `grep "ICACHE_ENTRIES =" $(src_dir)/riscv/mmu.h | sed 's/.* = \(.*\);/\1/'`
+
+icache.h: mmu.h
+	$(src_dir)/riscv/gen_icache $(icache_entries) > $@.tmp
 	mv $@.tmp $@
 
 $(riscv_gen_srcs): %.cc: insns/%.h insn_template.cc