From: Cesar Strauss <cestrauss@gmail.com>
Date: Tue, 16 Mar 2021 00:12:11 +0000 (-0300)
Subject: Define and initialise the mode variable, to be used later on
X-Git-Tag: convert-csv-opcode-to-binary~30
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=432430b45f5fb34fbbce85603301973f4f935a71;p=soc.git

Define and initialise the mode variable, to be used later on
---

diff --git a/src/soc/decoder/power_svp64_rm.py b/src/soc/decoder/power_svp64_rm.py
index 5c2b497e..ed1ed301 100644
--- a/src/soc/decoder/power_svp64_rm.py
+++ b/src/soc/decoder/power_svp64_rm.py
@@ -81,6 +81,7 @@ class SVP64RMModeDecode(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
+        mode = self.rm_in.mode
 
         # decode pieces of mode
         is_ldst = Signal()