From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 9 Apr 2021 14:26:21 +0000 (+0100)
Subject: add vst pre-pnr test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=43e4800a9ca9993d3a74729a1bce0c3e26335203;p=soc-cxxrtl-sim.git

add vst pre-pnr test
---

diff --git a/small_jtag_test/Makefile b/small_jtag_test/Makefile
index 2124e97..778623f 100644
--- a/small_jtag_test/Makefile
+++ b/small_jtag_test/Makefile
@@ -5,6 +5,12 @@ YOSYS_INCLUDE	= $(shell yosys-config --datdir)/include
 all: tb
 	./tb
 
+tb_ghdl: main.cpp add_ghdl.cpp
+	clang++ \
+    -DDESIGN=cxxrtl_design::p_add \
+    -DCXX_FILE=\"add_ghdl.cpp\" \
+    -g -O3 -std=c++14 -I $(YOSYS_INCLUDE) $< -o $@
+
 tb: main.cpp add.cpp
 	clang++ \
     -DDESIGN=cxxrtl_design::p_add \
diff --git a/small_jtag_test/freepdk_45/sff1r_x4.vhd b/small_jtag_test/freepdk_45/sff1r_x4.vhd
new file mode 100644
index 0000000..baf3cc0
--- /dev/null
+++ b/small_jtag_test/freepdk_45/sff1r_x4.vhd
@@ -0,0 +1,35 @@
+--
+-- Generated by VASY
+--
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+
+ENTITY sff1r_x4 IS
+PORT(
+  ck	: IN BIT;
+  i	: IN BIT;
+  nrst	: IN BIT;
+  q	: OUT BIT;
+  vdd	: IN BIT;
+  vss	: IN BIT
+);
+END sff1r_x4;
+
+ARCHITECTURE RTL OF sff1r_x4 IS
+  SIGNAL sff_m	: BIT;
+BEGIN
+  q <= sff_m;
+  PROCESS ( ck, nrst )
+  BEGIN
+    IF  ((ck = '1') AND ck'EVENT)
+    THEN 
+        IF (nrst = '1')
+        THEN sff_m <= i;
+        END IF;
+    END IF;
+    IF  ((nrst = '0') AND nrst'EVENT)
+    THEN sff_m <= '0';
+    END IF;
+  END PROCESS;
+END RTL;
diff --git a/small_jtag_test/vbe2vst.py b/small_jtag_test/vbe2vst.py
index 41bed78..7cf7541 100755
--- a/small_jtag_test/vbe2vst.py
+++ b/small_jtag_test/vbe2vst.py
@@ -13,12 +13,21 @@ VASY_CMD = "schroot -c coriolis -d /tmp -- ~/alliance/install/bin/vasy"
 ALLIANCEBASE = "../alliance-check-toolkit/cells"
 ALLIANCE_LIBS = ['nsxlib', 'niolib']
 
+yosys_ghdl_template = "ghdl --std=08 -g %s\n"
+yosys_ghdl_footer = """proc
+write_verilog %s.v
+write_ilang %s.il
+"""
+
 for libname in ALLIANCE_LIBS:
 
     NSXLIB = "%s/%s" % (ALLIANCEBASE, libname)
 
     os.system("mkdir -p %s" % libname)
 
+    # yosys ghdl loader script
+    ghdl_txt = "plugin -i ghdl\n"
+
     for fname in os.listdir(NSXLIB):
         if not fname.endswith(".vbe"):
             continue
@@ -27,4 +36,18 @@ for libname in ALLIANCE_LIBS:
         os.system("cp %s/%s /tmp" % (NSXLIB, fname))
         os.system("rm -f /tmp/%s.vhd" % (prefix))
         os.system("%s -s -I vbe %s %s" % (VASY_CMD, fname, prefix))
-        os.system("cp /tmp/%s.vhd %s/%s.vhdl" % (prefix, libname, prefix))
+        os.system("cp /tmp/%s.vhd %s" % (prefix, libname))
+        # add loader template for this module
+        if fname == 'sff1r_x4.vbe':
+            # don't ask.
+            #ghdl_txt += 'read_verilog freepdk_45/sff1r_x4.v\n'
+            os.system("cp freepdk_45/%s.vhd %s" % (prefix, libname))
+        ghdl_txt += yosys_ghdl_template % prefix
+
+    ghdl_txt += yosys_ghdl_footer % (libname, libname)
+
+    # write out the ghdl script
+    fname = "%s/ghdl.ys" % libname
+    print ("text to %s\n" % fname, ghdl_txt)
+    with open(fname, "w") as f:
+        f.write(ghdl_txt)
diff --git a/small_jtag_test/vhd2obj.py b/small_jtag_test/vhd2obj.py
new file mode 100755
index 0000000..31740ba
--- /dev/null
+++ b/small_jtag_test/vhd2obj.py
@@ -0,0 +1,28 @@
+#!/usr/bin/env python3
+
+"""builds nsxlib and other VHD files into object files using ghdl
+"""
+
+import os
+import sys
+
+SRC = [('nsxlib', 'vhd'),
+       ('niolib', 'vhd'),
+       ('vst_src', 'vst')]
+
+# make and change to obj dir
+os.system("mkdir -p obj")
+#cwd = os.getcwd()
+#os.chdir("obj")
+
+for srcdir, suffix in SRC:
+    # run ghdl -a on every vhd / vst file
+    for fname in os.listdir("%s" % srcdir):
+        if not fname.endswith(".%s" % suffix):
+            continue
+        print (fname)
+        prefix = fname[:-4] # strip ".vhd"
+        os.system("ghdl -a --std=08 %s/%s" % (srcdir, fname))
+
+# back to original dir
+#os.chdir(cwd)
diff --git a/small_jtag_test/vst_correct.py b/small_jtag_test/vst_correct.py
index 0aa3b7f..b8ea181 100755
--- a/small_jtag_test/vst_correct.py
+++ b/small_jtag_test/vst_correct.py
@@ -19,7 +19,7 @@ for fname in os.listdir("vst_src"):
     txt = txt.replace("linkage bit", "in bit")
     # and double-underscores
     txt = txt.replace("__", "_")
-    fname = fname[:-3] + "vhdl"
+    #fname = fname[:-3] + "vhdl"
     # write the file
     with open(fname, "w") as f:
         f.write(txt)