From: Luke Kenneth Casson Leighton Date: Thu, 30 Jun 2022 19:19:32 +0000 (+0100) Subject: add missing target remove text X-Git-Tag: opf_rfc_ls005_v1~1433 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4ae0db83fdd8e562a844bd4e74485135e4d5e26b;p=libreriscv.git add missing target remove text --- diff --git a/openpower/simple_v_spec.tex b/openpower/simple_v_spec.tex index d6d86060c..f837397bc 100644 --- a/openpower/simple_v_spec.tex +++ b/openpower/simple_v_spec.tex @@ -93,19 +93,21 @@ EU Grants 871528 and 957073. \tableofcontents -\chapter{Scalable Vectors for the Power ISA}\hypertarget{svux2fsv}{Scalable Vectors for the Power ISA} +\chapter{Scalable Vectors for the Power ISA} +\hypertarget{svux2fscalvecpowisa}{} +\hypertarget{SVux7csv}{} \input{tex_out/sv.tex} -\chapter{Overview}\hypertarget{svux2foverview}{Overview} +\chapter{Overview}\hypertarget{svux2foverview}{} \input{tex_out/overview.tex} \chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{Compliancy Levels} \input{tex_out/compliancy_levels.tex} -\chapter{SVP64}\hypertarget{svux2fsvp64}{SVP64} +\chapter{SVP64}\hypertarget{svux2fsvp64}{} \input{tex_out/svp64.tex} -\chapter{SPRs}\hypertarget{svux2fsprs}{SPRs} +\chapter{SPRs}\hypertarget{svux2fsprs}{} \input{tex_out/sprs.tex} -\chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{Arithmetic Mode} +\chapter{Arithmetic Mode}\hypertarget{svux2fnormal}{} \input{tex_out/normal.tex} -\chapter{Load/Store Mode}\hypertarget{svux2fldst}{Load/Store Mode} +\chapter{Load/Store Mode}\hypertarget{svux2fldst}{} \input{tex_out/ldst.tex} \chapter{Condition Register Fields Mode}\hypertarget{svux2fcr_ops}{Condition Register Fields Mode} \input{tex_out/cr_ops.tex}