From: Tobias Platen Date: Tue, 9 Mar 2021 17:06:59 +0000 (+0100) Subject: comment out broken spr code X-Git-Tag: convert-csv-opcode-to-binary~72 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4e3a0fc227ecf35ac73c1e6ab455bf86d2d228ba;p=soc.git comment out broken spr code --- diff --git a/src/soc/decoder/isa/radixmmu.py b/src/soc/decoder/isa/radixmmu.py index 93230d6a..c208fa09 100644 --- a/src/soc/decoder/isa/radixmmu.py +++ b/src/soc/decoder/isa/radixmmu.py @@ -169,10 +169,11 @@ class RADIX: def __init__(self, mem, caller): self.mem = mem self.caller = caller - self.dsisr = self.caller.spr["DSISR"] - self.dar = self.caller.spr["DAR"] - self.pidr = self.caller.spr["PIDR"] - self.prtbl = self.caller.spr["PRTBL"] + #TODO move to lookup + #self.dsisr = self.caller.spr["DSISR"] + #self.dar = self.caller.spr["DAR"] + #self.pidr = self.caller.spr["PIDR"] + #self.prtbl = self.caller.spr["PRTBL"] # cached page table stuff self.pgtbl0 = 0