From: Luke Kenneth Casson Leighton Date: Wed, 12 Feb 2020 15:10:00 +0000 (+0000) Subject: add bit of extra explanatory comment for carry-ripple thing X-Git-Tag: ls180-24jan2020~193 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=4eeab805e499c35c5d926f33ebd60b85b66679fc;p=ieee754fpu.git add bit of extra explanatory comment for carry-ripple thing --- diff --git a/src/ieee754/part_mul_add/adder.py b/src/ieee754/part_mul_add/adder.py index 2eb6de27..1ade9f84 100644 --- a/src/ieee754/part_mul_add/adder.py +++ b/src/ieee754/part_mul_add/adder.py @@ -261,6 +261,11 @@ class PartitionedAdder(Elaboratable): # special hardware on FPGAs comb += expanded_o.eq(expanded_a + expanded_b) + # ok now we have the carry-out, however because it's the MSB it's + # in the wrong position in the output as far as putting it into + # a chain of adds (or other operations). therefore we need to + # "ripple" carry-out down to the same position that carry-in is + # in [the LSB of each partition]. comb += ripple.results_in.eq(carry_tmp) comb += ripple.gates.eq(self.part_pts.as_sig()) comb += self.carry_out.eq(ripple.output)