From: Luke Kenneth Casson Leighton Date: Wed, 15 Jul 2020 15:07:53 +0000 (+0100) Subject: test privileged rfid call X-Git-Tag: div_pipeline~18 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=50cb750d7f20188be2230ccf0411470b1a187ad8;p=soc.git test privileged rfid call --- diff --git a/src/soc/config/endian.py b/src/soc/config/endian.py index eb6e0c3f..0aaa61c2 100644 --- a/src/soc/config/endian.py +++ b/src/soc/config/endian.py @@ -1,5 +1,5 @@ global bigendian -bigendian = 0 +bigendian = 1 def set_endian_mode(mode): bigendian = mode diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index 75d2d48e..146708ed 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -143,6 +143,16 @@ class TrapTestCase(FHDLTestCase): msr = 1 << MSR.PR # set in "problem state" self.run_tst_program(Program(lst, bigendian), initial_regs, initial_msr=msr) + def test_7_rfid_priv_0(self): + lst = ["rfid"] + initial_regs = [0] * 32 + initial_regs[1] = 1 + initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} + msr = 1 << MSR.PR # set in "problem state" + self.run_tst_program(Program(lst, bigendian), + initial_regs, initial_sprs, + initial_msr=msr) + def test_999_illegal(self): # ok, um this is a bit of a cheat: use an instruction we know # is not implemented by either ISACaller or the core