From: Luke Kenneth Casson Leighton Date: Fri, 29 Jan 2021 23:00:46 +0000 (+0000) Subject: increase register number sizes from 5 to 7 X-Git-Tag: convert-csv-opcode-to-binary~292 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=51c3a7242a8dceb76441e2e2141c749347277866;p=soc.git increase register number sizes from 5 to 7 --- diff --git a/src/soc/decoder/decode2execute1.py b/src/soc/decoder/decode2execute1.py index d7185326..75b66d36 100644 --- a/src/soc/decoder/decode2execute1.py +++ b/src/soc/decoder/decode2execute1.py @@ -92,11 +92,11 @@ class Decode2ToExecute1Type(RecordObject): if asmcode: self.asmcode = Signal(8, reset_less=True) # only for simulator - self.write_reg = Data(5, name="rego") - self.write_ea = Data(5, name="ea") # for LD/ST in update mode - self.read_reg1 = Data(5, name="reg1") - self.read_reg2 = Data(5, name="reg2") - self.read_reg3 = Data(5, name="reg3") + self.write_reg = Data(7, name="rego") + self.write_ea = Data(7, name="ea") # for LD/ST in update mode + self.read_reg1 = Data(7, name="reg1") + self.read_reg2 = Data(7, name="reg2") + self.read_reg3 = Data(7, name="reg3") self.write_spr = Data(SPR, name="spro") self.read_spr1 = Data(SPR, name="spr1") #self.read_spr2 = Data(SPR, name="spr2") # only one needed