From: Luke Kenneth Casson Leighton Date: Fri, 30 Mar 2018 13:04:18 +0000 (+0100) Subject: rework spec generation functions X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=53f5e6f669b1ad4239a07dea8705200d1bbf3f13;p=pinmux.git rework spec generation functions --- diff --git a/src/spec/interfaces.py b/src/spec/interfaces.py index 92f0c22..51d14b1 100644 --- a/src/spec/interfaces.py +++ b/src/spec/interfaces.py @@ -1,8 +1,8 @@ #!/usr/bin/env python +from spec.pinfunctions import pinspec from copy import deepcopy - def namesuffix(name, suffix, namelist): names = [] for n in namelist: @@ -21,91 +21,20 @@ class PinGen(object): self.fname = fname def __call__(self, suffix, offs, bank, mux, - spec=None, start=None, limit=None, origsuffix=None): + start=None, limit=None, spec=None, origsuffix=None): pingroup = self.pinfn(suffix, bank) + if isinstance(pingroup, tuple): + prefix, pingroup = pingroup + else: + prefix = self.fname + if start and limit: + limit = start + limit pingroup = pingroup[start:limit] - pins = Pins(self.fname, pingroup, self.bankspec, + pins = Pins(prefix, pingroup, self.bankspec, suffix, offs, bank, mux, spec, origsuffix=suffix) self.pinouts.pinmerge(pins) - -# define functions here - -def i2s(suffix, bank): - return ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'] - -def emmc(suffix, bank): - emmcpins = ['CMD+', 'CLK+'] - for i in range(8): - emmcpins.append("D%d*" % i) - return emmcpins - -def sdmmc(suffix, bank): - sdmmcpins = ['CMD+', 'CLK+'] - for i in range(4): - sdmmcpins.append("D%d*" % i) - return sdmmcpins - -def spi(suffix, bank): - return ['CLK*', 'NSS*', 'MOSI*', 'MISO*'] - -def quadspi(suffix, bank): - return ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*'] - -def i2c(suffix, bank): - return ['SDA*', 'SCL*'] - -def jtag(suffix, bank): - return ['MS+', 'DI-', 'DO+', 'CK+'] - -def uart(suffix, bank): - return ['TX+', 'RX-'] - -def ulpi(suffix, bank): - ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+'] - for i in range(8): - ulpipins.append('D%d*' % i) - return ulpipins - -def uartfull(suffix, bank): - return ['TX+', 'RX-', 'CTS-', 'RTS+'] - -def rgbttl(suffix, bank): - ttlpins = ['CK+', 'DE+', 'HS+', 'VS+'] - for i in range(24): - ttlpins.append("D%d+" % i) - return ttlpins - -def rgmii(suffix, bank): - buspins = [] - for i in range(4): - buspins.append("ERXD%d-" % i) - for i in range(4): - buspins.append("ETXD%d+" % i) - buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-', - 'EMDC+', 'EMDIO*', - 'ETXEN+', 'ETXCK+', 'ECRS-', - 'ECOL+', 'ETXERR+'] - return buspins - - -# list functions by name here - -pinspec = {'IIS': i2s, - 'MMC': emmc, - 'SD': sdmmc, - 'SPI': spi, - 'QSPI': quadspi, - 'TWI': i2c, - 'JTAG': jtag, - 'UART': uart, - 'UARTQ': uartfull, - 'LCD': rgbttl, - 'ULPI': ulpi, - 'RG': rgmii, - } - # pinouts class class Pinouts(object): @@ -113,7 +42,7 @@ class Pinouts(object): self.bankspec = bankspec self.pins = {} self.fnspec = {} - for fname, pinfn in pinspec.items(): + for fname, pinfn in pinspec: if isinstance(pinfn, tuple): name, pinfn = pinfn else: @@ -157,110 +86,6 @@ class Pinouts(object): def __getitem__(self, k): return self.pins[k] - def flexbus1(self, suffix, offs, bank, mux=1, spec=None, limit=None): - buspins = [] - for i in range(8): - buspins.append("AD%d*" % i) - for i in range(2): - buspins.append("CS%d+" % i) - buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+', - 'A0', 'A1', 'TS', 'TBST', - 'TSIZ0', 'TSIZ1'] - for i in range(4): - buspins.append("BWE%d" % i) - for i in range(2, 6): - buspins.append("CS%d+" % i) - pins = Pins('FB', buspins, self.bankspec, - suffix, offs, bank, mux, - spec, limit, origsuffix=suffix) - self.pinmerge(pins) - - def flexbus2(self, suffix, offs, bank, mux=1, spec=None, limit=None): - buspins = [] - for i in range(8, 32): - buspins.append("AD%d*" % i) - pins = Pins('FB', buspins, self.bankspec, - suffix, offs, bank, mux, - spec, limit, origsuffix=suffix) - self.pinmerge(pins) - - def sdram1(self, suffix, offs, bank, mux=1, spec=None): - buspins = [] - for i in range(16): - buspins.append("SDRDQM%d*" % i) - for i in range(12): - buspins.append("SDRAD%d+" % i) - for i in range(8): - buspins.append("SDRDQ%d+" % i) - for i in range(3): - buspins.append("SDRCS%d#+" % i) - for i in range(2): - buspins.append("SDRDQ%d+" % i) - for i in range(2): - buspins.append("SDRBA%d+" % i) - buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+', - 'SDRRST+'] - pins = Pins('SDR', buspins, self.bankspec, - suffix, offs, bank, mux, - spec, origsuffix=suffix) - self.pinmerge(pins) - - def sdram2(self, suffix, offs, bank, mux=1, spec=None, limit=None): - buspins = [] - for i in range(3, 6): - buspins.append("SDRCS%d#+" % i) - for i in range(8, 32): - buspins.append("SDRDQ%d*" % i) - pins = Pins('SDR', buspins, self.bankspec, - suffix, offs, bank, mux, - spec, limit, origsuffix=suffix) - self.pinmerge(pins) - - def mcu8080(self, suffix, offs, bank, mux=1, spec=None): - buspins = [] - for i in range(8): - buspins.append("MCUD%d*" % i) - for i in range(8): - buspins.append("MCUAD%d+" % (i + 8)) - for i in range(6): - buspins.append("MCUCS%d+" % i) - for i in range(2): - buspins.append("MCUNRB%d+" % i) - buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+', - 'MCURST+'] - pins = Pins('MCU', buspins, self.bankspec, - suffix, offs, bank, mux, - spec, origsuffix=suffix) - self.pinmerge(pins) - - def eint(self, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None): - gpiopins = [] - for i in range(gpiooffs, gpiooffs + gpionum): - gpiopins.append("%d*" % (i)) - pins = Pins('EINT', gpiopins, self.bankspec, - suffix, offs, bank, mux, - spec, origsuffix=suffix) - self.pinmerge(pins) - - def pwm(self, suffix, offs, bank, pwmoffs, pwmnum=1, mux=1, spec=None): - pwmpins = [] - for i in range(pwmoffs, pwmoffs + pwmnum): - pwmpins.append("%d+" % (i)) - pins = Pins('PWM', pwmpins, self.bankspec, - suffix, offs, bank, mux, - spec, origsuffix=suffix) - self.pinmerge(pins) - - def gpio(self, suffix, offs, bank, gpiooffs, gpionum=1, mux=1, spec=None): - prefix = "GPIO%s" % bank - gpiopins = [] - for i in range(gpiooffs, gpiooffs + gpionum): - gpiopins.append("%s%d*" % (bank, i)) - pins = Pins(prefix, gpiopins, self.bankspec, - suffix, offs, bank, mux, - spec, origsuffix=suffix) - self.pinmerge(pins) - def pinmerge(self, fn): # hack, store the function specs in the pins dict fname = fn.fname diff --git a/src/spec/m_class.py b/src/spec/m_class.py index 8c17642..3f3974b 100644 --- a/src/spec/m_class.py +++ b/src/spec/m_class.py @@ -25,48 +25,48 @@ def pinspec(): pinouts = Pinouts(bankspec) # Bank A, 0-15 - pinouts.gpio("", ('A', 0), "A", 0, 16, 0) + pinouts.gpio("", ('A', 0), "A", 0, 0, 16) pinouts.spi("0", ('A', 0), "A", 3) pinouts.uartfull("1", ('A', 0), "A", 2) pinouts.i2c("0", ('A', 4), "A", 2) pinouts.emmc("", ('A', 0), "A", 1) #pinouts.uart("0", ('A', 14), "A", 1) pinouts.spi("1", ('A', 6), "A", 2) - pinouts.eint("", ('A', 10), "A", 0, 6) - pinouts.eint("", ('A', 4), "A", 0, 6, mux=3) + pinouts.eint("", ('A', 10), "A", 1, start=0, limit=6) + pinouts.eint("", ('A', 4), "A", 3, start=0, limit=6) pinouts.sdmmc("0", ('A', 10), "A", 2) pinouts.jtag("0", ('A', 10), "A", 3) pinouts.uart("0", ('A', 14), "A", 3) # Bank B, 16-47 - pinouts.gpio("", ('B', 0), "B", 0, 28, 0) + pinouts.gpio("", ('B', 0), "B", 0, 0, 28) pinouts.rgbttl("0", ('B', 0), "B", 1) pinouts.spi("0", ('B', 12), "B", 2) pinouts.quadspi("", ('B', 4), "B", 2, limit=4) pinouts.uart("1", ('B', 16), "B", 2) pinouts.i2c("2", ('B', 18), "B", 2) - pinouts.pwm("", ('B', 9), "B", 0, 1, mux=2) - pinouts.pwm("", ('B', 20), "B", 1, 2, mux=2) + pinouts.pwm("", ('B', 9), "B", 2, start=0, limit=1) + pinouts.pwm("", ('B', 20), "B", 2, start=1, limit=2) pinouts.sdmmc("0", ('B', 22), "B", 2) - pinouts.eint("", ('B', 0), "B", 6, 4, mux=3) + pinouts.eint("", ('B', 0), "B", 3, start=6, limit=4) pinouts.flexbus2("", ('B', 4), "B", 3) pinouts.i2c("0", ('B', 0), "B", 2) pinouts.uart("0", ('B', 2), "B", 2) pinouts.uart("2", ('B', 10), "B", 2) # Bank C, 48-71 - pinouts.gpio("", ("C", 0), "C", 0, 24, 0) + pinouts.gpio("", ("C", 0), "C", 0, 0, 24) pinouts.ulpi("0", ('C', 0), "C", 1) pinouts.ulpi("1", ('C', 12), "C", 1) pinouts.spi("1", ('C', 8), "C", 2) #pinouts.spi("1", ('C', 28), "C", 2) pinouts.uartfull("0", ('C', 20), "C", 3) - pinouts.eint("", ('C', 0), "C", 10, 8, mux=3) + pinouts.eint("", ('C', 0), "C", 3, start=10, limit=8) pinouts.jtag("1", ('C', 8), "C", 3) - pinouts.eint("", ('C', 12), "C", 22, 8, mux=3) + pinouts.eint("", ('C', 12), "C", 3, start=22, limit=8) pinouts.uart("0", ('C', 22), "C", 2) pinouts.i2s("", ('C', 13), "C", 2) - pinouts.pwm("", ('C', 21), "C", 2, 1, mux=2) + pinouts.pwm("", ('C', 21), "C", 2, start=2, limit=1) # Bank D, 72-96 @@ -91,49 +91,49 @@ def pinspec(): 'FB_TSIZ1': ('FB_BWE1', 2, "D"), } #pinouts.mcu8080("", 72, "D", 1) - pinouts.gpio("", ('D', 0), "D", 0, 24, 0) + pinouts.gpio("", ('D', 0), "D", 0, 0, 24) pinouts.flexbus1("", ('D', 0), "D", 1, spec=flexspec) pinouts.i2c("1", ('D', 8), "D", 3) - pinouts.pwm("", ('D', 21), "D", 0, 3, mux=1) + pinouts.pwm("", ('D', 21), "D", 1, start=0, limit=3) pinouts.i2c("0", ('D', 10), "D", 3) pinouts.i2c("2", ('D', 19), "D", 2) pinouts.uartfull("0", ('D', 0), "D", 2) pinouts.uart("1", ('D', 21), "D", 2) pinouts.uart("2", ('D', 13), "D", 2) - pinouts.eint("", ('D', 19), "D", 18, 4, mux=3) - pinouts.eint("", ('D', 23), "D", 9, 1, mux=3) - pinouts.eint("", ('D', 13), "D", 5, 4, mux=3) - pinouts.eint("", ('D', 0), "D", 30, 2, mux=3) + pinouts.eint("", ('D', 19), "D", 3, start=18, limit=4) + pinouts.eint("", ('D', 23), "D", 3, start=9, limit=1) + pinouts.eint("", ('D', 13), "D", 3, start=5, limit=4) + pinouts.eint("", ('D', 0), "D", 3, start=30, limit=2) pinouts.i2c("1", ('D', 2), "D", 3) pinouts.sdmmc("1", ('D', 4), "D", 2) # Bank E - pinouts.gpio("", ('E', 0), "E", 0, 24, 0) + pinouts.gpio("", ('E', 0), "E", 0, 0, 24) pinouts.flexbus2("", ('E', 0), "E", 1) pinouts.sdmmc("1", ('E', 0), "E", 2) pinouts.sdmmc("2", ('E', 8), "E", 2) pinouts.quadspi("", ('E', 18), "E", 2) pinouts.uartfull("1", ('E', 14), "E", 2) pinouts.i2c("1", ('E', 6), "E", 2) - pinouts.eint("", ('E', 0), "E", 10, 8, mux=3) - pinouts.eint("", ('E', 8), "E", 22, 6, mux=3) + pinouts.eint("", ('E', 0), "E", 3, start=10, limit=8) + pinouts.eint("", ('E', 8), "E", 3, start=22, limit=6) pinouts.emmc("", ('E', 14), "E", 3) # Bank F - pinouts.gpio("", ('F', 0), "F", 0, 10, 0) + pinouts.gpio("", ('F', 0), "F", 0, 0, 10) pinouts.i2s("", ('F', 0), "F", 1) pinouts.i2c("0", ('F', 6), "F", 2) - pinouts.pwm("", ('F', 8), "F", 0, 1, mux=2) - pinouts.pwm("", ('F', 9), "F", 1, 1, mux=2) + pinouts.pwm("", ('F', 8), "F", 2, start=0, limit=1) + pinouts.pwm("", ('F', 9), "F", 2, start=1, limit=1) pinouts.uart("2", ('F', 8), "F", 1) pinouts.sdmmc("2", ('F', 0), "F", 2) - pinouts.eint("", ('F', 0), "F", 18, 4, mux=3) - pinouts.pwm("", ('F', 4), "F", 2, 1, mux=3) - pinouts.eint("", ('F', 5), "F", 7, 1, mux=3) - pinouts.eint("", ('F', 6), "F", 28, 4, mux=3) + pinouts.eint("", ('F', 0), "F", 3, start=18, limit=4) + pinouts.pwm("", ('F', 4), "F", 3, start=2, limit=1) + pinouts.eint("", ('F', 5), "F", 3, start=7, limit=1) + pinouts.eint("", ('F', 6), "F", 3, start=28, limit=4) # Bank G - pinouts.gpio("", ('G', 0), "G", 0, 32, 0) + pinouts.gpio("", ('G', 0), "G", 0, 0, 32) pinouts.rgmii("", ('G', 0), "G", 1) pinouts.ulpi("2", ('G', 20), "G", 1) pinouts.rgbttl("1", ('G', 0), "G", 2) diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py new file mode 100644 index 0000000..d41a354 --- /dev/null +++ b/src/spec/pinfunctions.py @@ -0,0 +1,164 @@ +#!/usr/bin/env python + +def i2s(suffix, bank): + return ['MCK+', 'BCK+', 'LRCK+', 'DI-', 'DO+'] + +def emmc(suffix, bank): + emmcpins = ['CMD+', 'CLK+'] + for i in range(8): + emmcpins.append("D%d*" % i) + return emmcpins + +def sdmmc(suffix, bank): + sdmmcpins = ['CMD+', 'CLK+'] + for i in range(4): + sdmmcpins.append("D%d*" % i) + return sdmmcpins + +def spi(suffix, bank): + return ['CLK*', 'NSS*', 'MOSI*', 'MISO*'] + +def quadspi(suffix, bank): + return ['CK*', 'NSS*', 'IO0*', 'IO1*', 'IO2*', 'IO3*'] + +def i2c(suffix, bank): + return ['SDA*', 'SCL*'] + +def jtag(suffix, bank): + return ['MS+', 'DI-', 'DO+', 'CK+'] + +def uart(suffix, bank): + return ['TX+', 'RX-'] + +def ulpi(suffix, bank): + ulpipins = ['CK+', 'DIR+', 'STP+', 'NXT+'] + for i in range(8): + ulpipins.append('D%d*' % i) + return ulpipins + +def uartfull(suffix, bank): + return ['TX+', 'RX-', 'CTS-', 'RTS+'] + +def rgbttl(suffix, bank): + ttlpins = ['CK+', 'DE+', 'HS+', 'VS+'] + for i in range(24): + ttlpins.append("D%d+" % i) + return ttlpins + +def rgmii(suffix, bank): + buspins = [] + for i in range(4): + buspins.append("ERXD%d-" % i) + for i in range(4): + buspins.append("ETXD%d+" % i) + buspins += ['ERXCK-', 'ERXERR-', 'ERXDV-', + 'EMDC+', 'EMDIO*', + 'ETXEN+', 'ETXCK+', 'ECRS-', + 'ECOL+', 'ETXERR+'] + return buspins + +def flexbus1(suffix, bank): + buspins = [] + for i in range(8): + buspins.append("AD%d*" % i) + for i in range(2): + buspins.append("CS%d+" % i) + buspins += ['ALE', 'OE', 'RW', 'TA', 'CLK+', + 'A0', 'A1', 'TS', 'TBST', + 'TSIZ0', 'TSIZ1'] + for i in range(4): + buspins.append("BWE%d" % i) + for i in range(2, 6): + buspins.append("CS%d+" % i) + return buspins + +def flexbus2(suffix, bank): + buspins = [] + for i in range(8, 32): + buspins.append("AD%d*" % i) + return buspins + +def sdram1(suffix, bank): + buspins = [] + for i in range(16): + buspins.append("SDRDQM%d*" % i) + for i in range(12): + buspins.append("SDRAD%d+" % i) + for i in range(8): + buspins.append("SDRDQ%d+" % i) + for i in range(3): + buspins.append("SDRCS%d#+" % i) + for i in range(2): + buspins.append("SDRDQ%d+" % i) + for i in range(2): + buspins.append("SDRBA%d+" % i) + buspins += ['SDRCKE+', 'SDRRAS#+', 'SDRCAS#+', 'SDRWE#+', + 'SDRRST+'] + return buspins + +def sdram2(suffix, bank): + buspins = [] + for i in range(3, 6): + buspins.append("SDRCS%d#+" % i) + for i in range(8, 32): + buspins.append("SDRDQ%d*" % i) + return buspins + +def mcu8080(suffix, bank): + buspins = [] + for i in range(8): + buspins.append("MCUD%d*" % i) + for i in range(8): + buspins.append("MCUAD%d+" % (i + 8)) + for i in range(6): + buspins.append("MCUCS%d+" % i) + for i in range(2): + buspins.append("MCUNRB%d+" % i) + buspins += ['MCUCD+', 'MCURD+', 'MCUWR+', 'MCUCLE+', 'MCUALE+', + 'MCURST+'] + return buspins + +class RangePin(object): + def __init__(self, suffix, prefix=None): + self.suffix = suffix + self.prefix = prefix or '' + + def __getitem__(self, s): + res = [] + for idx in range(s.start or 0, s.stop or -1, s.step or 1): + res.append("%s%d%s" % (self.prefix, idx, self.suffix)) + return res + +def eint(suffix, bank): + return RangePin("*") + +def pwm(suffix, bank): + return RangePin("+") + +def gpio(suffix, bank): + return ("GPIO%s" % bank, RangePin(prefix=bank, suffix="*")) + + +# list functions by name here + +pinspec = (('IIS', i2s), + ('MMC', emmc), + ('SD', sdmmc), + ('SPI', spi), + ('QSPI', quadspi), + ('TWI', i2c), + ('JTAG', jtag), + ('UART', uart), + ('UARTQ', uartfull), + ('LCD', rgbttl), + ('ULPI', ulpi), + ('RG', rgmii), + ('FB', flexbus1), + ('FB', flexbus2), + ('SDR', sdram1), + ('SDR', sdram2), + ('EINT', eint), + ('PWM', pwm), + ('GPIO', gpio), + ) +