From: Wesley W. Terpstra Date: Mon, 30 Jan 2017 19:33:30 +0000 (-0800) Subject: xilinx ip: adjust to new diplomacy API X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b6760394d963b7d3f835c4c79ed73dd2bff2e6a;p=sifive-blocks.git xilinx ip: adjust to new diplomacy API --- diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala index 494d787..4a64766 100644 --- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala +++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala @@ -3,10 +3,10 @@ package sifive.blocks.devices.xilinxvc707pciex1 import Chisel._ import diplomacy.LazyModule -import rocketchip.{L2Crossbar,L2CrossbarModule,L2CrossbarBundle} +import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle} import uncore.tilelink2.TLWidthWidget -trait PeripheryXilinxVC707PCIeX1 extends L2Crossbar { +trait PeripheryXilinxVC707PCIeX1 extends TopNetwork { val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) l2.node := xilinxvc707pcie.master @@ -15,11 +15,11 @@ trait PeripheryXilinxVC707PCIeX1 extends L2Crossbar { intBus.intnode := xilinxvc707pcie.intnode } -trait PeripheryXilinxVC707PCIeX1Bundle extends L2CrossbarBundle { +trait PeripheryXilinxVC707PCIeX1Bundle extends TopNetworkBundle { val xilinxvc707pcie = new XilinxVC707PCIeX1IO } -trait PeripheryXilinxVC707PCIeX1Module extends L2CrossbarModule { +trait PeripheryXilinxVC707PCIeX1Module extends TopNetworkModule { val outer: PeripheryXilinxVC707PCIeX1 val io: PeripheryXilinxVC707PCIeX1Bundle diff --git a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala index a7cf844..fabfe30 100644 --- a/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala +++ b/src/main/scala/ip/xilinx/vc707axi_to_pcie_x1/vc707axi_to_pcie_x1.scala @@ -167,27 +167,27 @@ class vc707axi_to_pcie_x1() extends BlackBox class VC707AXIToPCIeX1(implicit p:Parameters) extends LazyModule { - val slave = AXI4SlaveNode(AXI4SlavePortParameters( + val slave = AXI4SlaveNode(Seq(AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( address = List(AddressSet(0x60000000L, 0x1fffffffL)), executable = true, supportsWrite = TransferSizes(1, 256), supportsRead = TransferSizes(1, 256), interleavedId = Some(0))), // the Xilinx IP is friendly - beatBytes = 8)) + beatBytes = 8))) - val control = AXI4SlaveNode(AXI4SlavePortParameters( + val control = AXI4SlaveNode(Seq(AXI4SlavePortParameters( slaves = Seq(AXI4SlaveParameters( address = List(AddressSet(0x50000000L, 0x03ffffffL)), supportsWrite = TransferSizes(1, 4), supportsRead = TransferSizes(1, 4), interleavedId = Some(0))), // no read interleaving b/c AXI-lite - beatBytes = 4)) + beatBytes = 4))) - val master = AXI4MasterNode(AXI4MasterPortParameters( + val master = AXI4MasterNode(Seq(AXI4MasterPortParameters( masters = Seq(AXI4MasterParameters( id = IdRange(0, 1), - aligned = false)))) + aligned = false))))) lazy val module = new LazyModuleImp(this) { // The master on the control port must be AXI-lite