From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 14 Jul 2020 19:31:49 +0000 (+0100)
Subject: update docstrings
X-Git-Tag: div_pipeline~38
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bf2d51f3735f89070746f5caa77fc7603859c25;p=soc.git

update docstrings
---

diff --git a/src/soc/fu/README.md b/src/soc/fu/README.md
index dc09399f..83198f16 100644
--- a/src/soc/fu/README.md
+++ b/src/soc/fu/README.md
@@ -4,7 +4,7 @@ In this directory are the pipelines.  The structure of each pipeline is
 as follows:
 
 * pipe_data.py: contains pipeline input and output data structures
-* XXXX_stage.py: files with function-specific stages
+* XXXX_stage.py: function-specific stages (connected up together by pipeline.py)
 * XXX_input_record.py: a PowerISA decoded instruction subset for this pipeline
 * pipeline.py: the actual pipeline chain, which brings all stages together
 
@@ -16,9 +16,9 @@ in its entirety from start to finish, including receiving of all
 operands and the storage of all results. AT NO TIME does a Comp Unit
 "abandon" data to a pipeline.
 
-Each pipeline is given a Como Umit frontend.  The base class uses regsoecs
-to construct the required latches in order to send and receive dsta to
-and from the required Register Files.
+Each pipeline is given a Comp Unit frontend.  The base class uses regspecs
+to construct the required latches in order to capture data pending send and
+receive data to and from the required Register Files.
 
 # Common files
 
diff --git a/src/soc/fu/spr/pipe_data.py b/src/soc/fu/spr/pipe_data.py
index f4b62aef..f7b28a25 100644
--- a/src/soc/fu/spr/pipe_data.py
+++ b/src/soc/fu/spr/pipe_data.py
@@ -7,6 +7,7 @@ the data structures are slightly more involved than just "INT, SPR".
 Links:
 * https://bugs.libre-soc.org/show_bug.cgi?id=348
 * https://libre-soc.org/openpower/isa/sprset/
+* https://libre-soc.org/3d_gpu/architecture/regfile/
 """
 
 from soc.fu.pipe_data import IntegerData