From: Jannis Harder Date: Mon, 9 May 2022 14:07:39 +0000 (+0200) Subject: Merge pull request #3297 from jix/sva_nested_clk_else X-Git-Tag: divfloor-in-write_smt2-old-test~33 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd;p=yosys.git Merge pull request #3297 from jix/sva_nested_clk_else verific: Fix conditions of SVAs with explicit clocks within procedures --- 5ca2ee0c3114464c91743b73efd7c4c4f15fb0dd