From: Michael Nolan Date: Sat, 4 Apr 2020 20:02:50 +0000 (-0400) Subject: Minor changes to test for caller.py, still not working at all X-Git-Tag: div_pipeline~1522 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5d3a36fc697ec083c1d0f92bed54cd4d2c911dac;p=soc.git Minor changes to test for caller.py, still not working at all --- diff --git a/libreriscv b/libreriscv index d38dcfdc..6c7c3167 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit d38dcfdcc6923a03b8b3ac0ff8d03781dc6e7e80 +Subproject commit 6c7c31673fad55da82c22fbbcac3f9b5c49e6cc7 diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 7bd2ca21..f177042d 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -55,7 +55,7 @@ class GPR(dict): class ISACaller: - # decoder2 - an instance of power_decoder2 + # decoder2 - an instance of power_decoder2 # regfile - a list of initial values for the registers def __init__(self, decoder2, regfile): self.gpr = GPR(decoder2, regfile) @@ -63,11 +63,16 @@ class ISACaller: self.namespace = {'GPR': self.gpr, 'MEM': self.mem, 'memassign': self.memassign - } + } def memassign(self, ea, sz, val): self.mem.memassign(ea, sz, val) + def call(self, name): + function, read_regs, uninit_regs, write_regs = self.instrs[name] + + + def inject(context): """ Decorator factory. """ diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 783f6886..9d693a42 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -42,7 +42,7 @@ class DecoderTestCase(FHDLTestCase): instruction = Signal(32) pdecode = create_pdecode() - simulator = ISACaller(pdecode, [0] * 32) + simulator = fixedarith(pdecode, [0] * 32) m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) comb += pdecode2.dec.raw_opcode_in.eq(instruction) @@ -50,15 +50,17 @@ class DecoderTestCase(FHDLTestCase): gen = generator.generate_instructions() def process(): - for ins in gen: + for ins, code in zip(gen, generator.assembly.splitlines()): print("0x{:X}".format(ins & 0xffffffff)) + print(code) # ask the decoder to decode this binary data (endian'd) yield pdecode2.dec.bigendian.eq(0) # little / big? yield instruction.eq(ins) # raw binary instr. yield Delay(1e-6) - yield from simulator.execute_op(pdecode2) + opname = code.split(' ')[0] + yield from simulator.call(opname) sim.add_process(process) with sim.write_vcd("simulator.vcd", "simulator.gtkw", @@ -67,7 +69,7 @@ class DecoderTestCase(FHDLTestCase): return simulator def test_addi(self): - lst = ["addi 1, 0, 0x1234",] + lst = ["addi 1, 0, 0x1234"] with Program(lst) as program: self.run_test_program(program)