From: Luke Kenneth Casson Leighton Date: Thu, 14 Apr 2022 11:47:24 +0000 (+0100) Subject: 80 char limit, remove creation of stall from ack/cyc, it has to be X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5e908c417ed4e6e12d262ab892da35c40509dcf0;p=soc.git 80 char limit, remove creation of stall from ack/cyc, it has to be done in the parent because that is what knows the usage --- diff --git a/src/soc/bus/wb_async.py b/src/soc/bus/wb_async.py index 60844e56..6775427f 100644 --- a/src/soc/bus/wb_async.py +++ b/src/soc/bus/wb_async.py @@ -135,16 +135,6 @@ class WBAsyncBridge(Elaboratable): i_wbs_rty_i=slave_rty ); - # Synthesize STALL signal for master port - if hasattr(self.master_bus, "stall"): - comb += self.master_bus.stall.eq(self.master_bus.cyc & ~self.master_bus.ack) - - # Convert incoming slave STALL signal to a format that the async bridge understands... - if hasattr(self.slave_bus, "stall"): - comb += slave_ack.eq(self.slave_bus.ack & ~self.slave_bus.stall) - else: - comb += slave_ack.eq(self.slave_bus.ack) - # Wire unused signals to 0 comb += slave_err.eq(0) comb += slave_rty.eq(0) @@ -154,13 +144,19 @@ class WBAsyncBridge(Elaboratable): return m def ports(self): - return [self.master_bus.adr, self.master_bus.dat_w, self.master_bus.dat_r, - self.master_bus.we, self.master_bus.sel, self.master_bus.stb, - self.master_bus.cyc, self.master_bus.ack, self.master_bus.err, + return [self.master_bus.adr, self.master_bus.dat_w, + self.master_bus.dat_r, + self.master_bus.we, self.master_bus.sel, + self.master_bus.stb, + self.master_bus.cyc, self.master_bus.ack, + self.master_bus.err, self.master_bus.rty, - self.slave_bus.adr, self.slave_bus.dat_w, self.slave_bus.dat_r, - self.slave_bus.we, self.slave_bus.sel, self.slave_bus.stb, - self.slave_bus.cyc, self.slave_bus.ack, self.slave_bus.err, + self.slave_bus.adr, self.slave_bus.dat_w, + self.slave_bus.dat_r, + self.slave_bus.we, self.slave_bus.sel, + self.slave_bus.stb, + self.slave_bus.cyc, self.slave_bus.ack, + self.slave_bus.err, self.slave_bus.rty ] @@ -177,4 +173,4 @@ def create_verilog(dut, ports, test_name): if __name__ == "__main__": wbasyncbridge = WBAsyncBridge(name="wbasyncbridge_0", address_width=30, data_width=32, granularity=8) - create_ilang(wbasyncbridge, wbasyncbridge.ports(), "wbasyncbridge_0") \ No newline at end of file + create_ilang(wbasyncbridge, wbasyncbridge.ports(), "wbasyncbridge_0")