From: sadoon Date: Fri, 25 Aug 2023 11:46:49 +0000 (+0100) Subject: (no commit message) X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5fc0eee9cd102936420e99572a7453b5a24ba7a1;p=libreriscv.git --- diff --git a/SFFS/gentoo_bootstrap.mdwn b/SFFS/gentoo_bootstrap.mdwn index 1fd890097..96d20f45d 100644 --- a/SFFS/gentoo_bootstrap.mdwn +++ b/SFFS/gentoo_bootstrap.mdwn @@ -93,7 +93,7 @@ To verify that our buildflags were applied by the build tools and respected by t This is not a perfect solution and the proper way would be either to: - Simulate an SFFS compliant chip running this code such as [Microwatt](https://libre-soc.org/HDL_workflow/microwatt/) (very time consuming) -- Use a softcore FPGA core or ASIC of Microwatt / LibreSOC to run this code (doable, FPGA softcore in progress [link to bug](link)) +- Use a softcore FPGA core or ASIC of Microwatt / LibreSOC to run this code (doable, FPGA softcore in progress [in progress](https://bugs.libre-soc.org/show_bug.cgi?id=1037)) - Use the finalized Libre-SOC chip (doable once it is ready) Also note that this only tests for a subset of VSX instructions at the moment, more will be added in the future, this is simply a quick test to run before attempting to run on simulation and/or a softcore as both can be somewhat time consuming. In other words, if this test gives any VSX instructions, don't attempt to run the code in simulation or a softcore to avoid wasting precious time.