From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 26 Nov 2018 00:50:59 +0000 (+0000)
Subject: fetch output state class
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=600909aff847cb0c54b4bc20bfc22c32239e26b1;p=rv32.git

fetch output state class
---

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 3eae2ad..e3a3467 100644
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -46,7 +46,7 @@ class CPUFetchStage(Module):
         self.output_pc = Signal(32, reset=self.reset_vector)
         self.output_instruction = Signal(32)
         self.output_state = Signal(fetch_output_state,
-                                   reset=fetch_output_state_empty)
+                                   reset=FOS.empty)
 
         #self.comb += [
         #    self.cd_sys.clk.eq(self.clk),
@@ -61,7 +61,7 @@ class CPUFetchStage(Module):
         self.comb += self.memory_interface_fetch_address.eq(fetch_pc[2:])
 
         #initial output_pc <= self.reset_vector;
-        #initial output_state <= `fetch_output_state_empty;
+        #initial output_state <= `FOS.empty;
 
         delayed_instruction = Signal(32, reset=0)
         delayed_instruction_valid = Signal(reset=0)
@@ -81,26 +81,26 @@ class CPUFetchStage(Module):
             FA.ack_trap:
                 If(self.memory_interface_fetch_valid,
                    [fetch_pc.eq(fetch_pc + 4),
-                    self.output_state.eq(fetch_output_state_valid)]
+                    self.output_state.eq(FOS.valid)]
                 ).Else(
                    [fetch_pc.eq(self.mtvec),
-                    self.output_state.eq(fetch_output_state_trap)]
+                    self.output_state.eq(FOS.trap)]
                 ),
             FA.fence:
                 [ fetch_pc.eq(self.output_pc + 4),
-                  self.output_state.eq(fetch_output_state_empty)
+                  self.output_state.eq(FOS.empty)
                 ],
             FA.jump:
                 [ fetch_pc.eq(self.target_pc),
-                  self.output_state.eq(fetch_output_state_empty)
+                  self.output_state.eq(FOS.empty)
                 ],
             FA.error_trap:
                    [fetch_pc.eq(self.mtvec),
-                    self.output_state.eq(fetch_output_state_empty)
+                    self.output_state.eq(FOS.empty)
                 ],
             FA.wait:
                    [fetch_pc.eq(fetch_pc),
-                    self.output_state.eq(fetch_output_state_valid)
+                    self.output_state.eq(FOS.valid)
                 ]
         }
         fc[FA.default] = fc[FA.ack_trap]
diff --git a/cpudefs.py b/cpudefs.py
index f4598df..b5217f9 100644
--- a/cpudefs.py
+++ b/cpudefs.py
@@ -39,9 +39,12 @@ class FA:
 
 fetch_output_state = 2
 
-fetch_output_state_empty = Constant(0x0, fetch_output_state)
-fetch_output_state_valid = Constant(0x1, fetch_output_state)
-fetch_output_state_trap = Constant(0x2, fetch_output_state)
+class FOS:
+    """ Fetch output state constants
+    """
+    empty = Constant(0x0, fetch_output_state)
+    valid = Constant(0x1, fetch_output_state)
+    trap = Constant(0x2, fetch_output_state)
 
 decode_action = 12