From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 17 Aug 2020 09:59:49 +0000 (+0100)
Subject: turn SelectableInt less/greater into signed versions.
X-Git-Tag: semi_working_ecp5~303
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=689512c89a16b3c50367c8112164a47a5f7c0977;p=soc.git

turn SelectableInt less/greater into signed versions.
may have ramifications as use of these operators assumes
unsigned
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 59728a0b..31ef3450 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -16,7 +16,7 @@ from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)
 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
                                      insns, MicrOp)
-from soc.decoder.helpers import exts
+from soc.decoder.helpers import exts, gtu, ltu
 from soc.consts import PIb, MSRb  # big-endian (PowerISA versions)
 
 from collections import namedtuple
@@ -423,7 +423,7 @@ class ISACaller:
         gts = []
         for x in inputs:
             print("gt input", x, output)
-            gt = (x > output)
+            gt = (gtu(x, output))
             gts.append(gt)
         print(gts)
         cy = 1 if any(gts) else 0
@@ -435,7 +435,7 @@ class ISACaller:
         gts = []
         for x in inputs:
             print("input", x, output)
-            gt = (x[32:64] > output[32:64]) == SelectableInt(1, 1)
+            gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
             gts.append(gt)
         cy32 = 1 if any(gts) else 0
         if not (2 & already_done):
diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index ebb8f3db..b1f150c6 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -280,6 +280,7 @@ class CryIn(Enum):
     ZERO = 0
     ONE = 1
     CA = 2
+    # TODO OV = 3
 
 
 @unique
diff --git a/src/soc/decoder/selectable_int.py b/src/soc/decoder/selectable_int.py
index 4e091ea3..700a6206 100644
--- a/src/soc/decoder/selectable_int.py
+++ b/src/soc/decoder/selectable_int.py
@@ -153,7 +153,6 @@ class FieldSelectableIntTestCase(unittest.TestCase):
         fs[0:2] = 0b10
         self.assertEqual(fs.get_range(), 0b1011)
 
-
 class SelectableInt:
     """SelectableInt - a class that behaves exactly like python int
 
@@ -177,6 +176,16 @@ class SelectableInt:
         self.value = b.value
         self.bits = b.bits
 
+    def to_signed_int(self):
+        print ("to signed?", self.value & (1<<(self.bits-1)), self.value)
+        if self.value & (1<<(self.bits-1)) != 0: # negative
+            res = self.value - (1<<self.bits)
+            print ("    val -ve:", self.bits, res)
+        else:
+            res = self.value
+            print ("    val +ve:", res)
+        return res
+
     def _op(self, op, b):
         if isinstance(b, int):
             b = SelectableInt(b, self.bits)
@@ -320,9 +329,9 @@ class SelectableInt:
         if isinstance(other, SelectableInt):
             other = check_extsign(self, other)
             assert other.bits == self.bits
-            other = other.value
+            other = other.to_signed_int()
         if isinstance(other, int):
-            return onebit(self.value >= other.value)
+            return onebit(self.to_signed_int() >= other)
         assert False
 
     def __le__(self, other):
@@ -331,9 +340,9 @@ class SelectableInt:
         if isinstance(other, SelectableInt):
             other = check_extsign(self, other)
             assert other.bits == self.bits
-            other = other.value
+            other = other.to_signed_int()
         if isinstance(other, int):
-            return onebit(self.value <= other)
+            return onebit(self.to_signed_int() <= other)
         assert False
 
     def __gt__(self, other):
@@ -342,20 +351,24 @@ class SelectableInt:
         if isinstance(other, SelectableInt):
             other = check_extsign(self, other)
             assert other.bits == self.bits
-            other = other.value
+            other = other.to_signed_int()
         if isinstance(other, int):
-            return onebit(self.value > other)
+            return onebit(self.to_signed_int() > other)
         assert False
 
     def __lt__(self, other):
+        print ("SelectableInt lt", self, other)
         if isinstance(other, FieldSelectableInt):
             other = other.get_range()
         if isinstance(other, SelectableInt):
             other = check_extsign(self, other)
             assert other.bits == self.bits
-            other = other.value
+            other = other.to_signed_int()
         if isinstance(other, int):
-            return onebit(self.value < other)
+            a = self.to_signed_int()
+            res = onebit(a  < other)
+            print ("    a < b", a, other, res)
+            return res
         assert False
 
     def __eq__(self, other):
@@ -366,6 +379,7 @@ class SelectableInt:
             other = check_extsign(self, other)
             assert other.bits == self.bits
             other = other.value
+        print ("    eq", other, self.value, other == self.value)
         if isinstance(other, int):
             return onebit(other == self.value)
         assert False
diff --git a/src/soc/fu/common_input_stage.py b/src/soc/fu/common_input_stage.py
index 4dbb5c07..745be772 100644
--- a/src/soc/fu/common_input_stage.py
+++ b/src/soc/fu/common_input_stage.py
@@ -40,6 +40,9 @@ class CommonInputStage(PipeModBase):
                     comb += self.o.xer_ca.eq(0b11) # XER CA/CA32
                 with m.Case(CryIn.CA):
                     comb += self.o.xer_ca.eq(self.i.xer_ca)
+                # XXX TODO
+                #with m.Case(CryIn.OV):
+                #    comb += self.o.xer_ca.eq(self.i.xer_ov)
 
         ##### sticky overflow and context (both pass-through) #####