From: Jędrzej Boczar <jboczar@antmicro.com>
Date: Wed, 22 Jul 2020 13:55:49 +0000 (+0200)
Subject: soc/integration: add bus standard parser arguments
X-Git-Tag: 24jan2021_ls180~64^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=706bc25dc1f2f123d10ed6e4d6eac0f24bb1e486;p=litex.git

soc/integration: add bus standard parser arguments
---

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index 043bc0aa..f88fbf92 100644
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -251,6 +251,17 @@ class SoCCore(LiteXSoC):
 # SoCCore arguments --------------------------------------------------------------------------------
 
 def soc_core_args(parser):
+    # Bus parameters
+    parser.add_argument("--bus-standard", default="wishbone",
+                        help="select bus standard: {}, (default=wishbone)".format(
+                            ", ".join(SoCBusHandler.supported_standard)))
+    parser.add_argument("--bus-data-width", default=32, type=auto_int,
+                        help="Bus data width (default=32)")
+    parser.add_argument("--bus-address-width", default=32, type=auto_int,
+                        help="Bus address width (default=32)")
+    parser.add_argument("--bus-timeout", default=1e6, type=float,
+                        help="Bus timeout in cycles (default=1e6)")
+
     # CPU parameters
     parser.add_argument("--cpu-type", default=None,
                         help="select CPU: {}, (default=vexriscv)".format(", ".join(iter(cpu.CPUS.keys()))))
diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 6d00ca64..646f36e3 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -1043,7 +1043,8 @@ class AXILiteDecoder(Module):
     {slaves}
     """.format(slaves=_doc_slaves)
 
-    def __init__(self, master, slaves):
+    def __init__(self, master, slaves, register=False):
+        # TODO: unused register argument
         addr_shift = log2_int(master.data_width//8)
 
         channels = {
@@ -1124,7 +1125,7 @@ class AXILiteInterconnectShared(Module):
     {slaves}
     """.format(slaves=AXILiteDecoder._doc_slaves)
 
-    def __init__(self, masters, slaves, timeout_cycles=1e6):
+    def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
         # TODO: data width
         shared = AXILiteInterface()
         self.submodules.arbiter = AXILiteArbiter(masters, shared)
@@ -1140,7 +1141,7 @@ class AXILiteCrossbar(Module):
     {slaves}
     """.format(slaves=AXILiteDecoder._doc_slaves)
 
-    def __init__(self, masters, slaves, timeout_cycles=1e6):
+    def __init__(self, masters, slaves, register=False, timeout_cycles=1e6):
         matches, busses = zip(*slaves)
         access_m_s = [[AXILiteInterface() for j in slaves] for i in masters]  # a[master][slave]
         access_s_m = list(zip(*access_m_s))  # a[slave][master]