From: Luke Kenneth Casson Leighton Date: Sat, 17 Nov 2018 06:58:42 +0000 (+0000) Subject: fix up c_lwsp and predicated test X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7269a5580079df2c78f1d859a4436355c6a21692;p=riscv-tests.git fix up c_lwsp and predicated test --- diff --git a/isa/rv64uc/sv_c_lwsp.S b/isa/rv64uc/sv_c_lwsp.S index a642203..81503a4 100644 --- a/isa/rv64uc/sv_c_lwsp.S +++ b/isa/rv64uc/sv_c_lwsp.S @@ -23,7 +23,7 @@ RVTEST_CODE_BEGIN SET_SV_MVL(3) SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1), - SV_REG_CSR(1, 2, 0, 28, 1) ) + SV_REG_CSR(1, 2, 0, 28, 0) ) SET_SV_VL(3) # store addr of data in x28 because CSR redirects x2 to x28 @@ -57,7 +57,7 @@ RVTEST_CODE_BEGIN SET_SV_MVL(3) SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1), - SV_REG_CSR(1, 2, 0, 2, 1) ) + SV_REG_CSR(1, 2, 0, 2, 0) ) SET_SV_VL(3) mv a1, sp diff --git a/isa/rv64uc/sv_c_lwsp_predication.S b/isa/rv64uc/sv_c_lwsp_predication.S index 0885dd7..ab06448 100644 --- a/isa/rv64uc/sv_c_lwsp_predication.S +++ b/isa/rv64uc/sv_c_lwsp_predication.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN SET_SV_MVL(3) SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1), - SV_REG_CSR(1, 2, 0, 2, 1) ) + SV_REG_CSR(1, 2, 0, 2, 0) ) SET_SV_2PREDCSRS( SV_PRED_CSR(1, 2, 0, 0, 10, 0), SV_PRED_CSR(1, 12, 0, 0, 11, 0) ); diff --git a/isa/rv64ui/sv_ld_elwidth_offs.S b/isa/rv64ui/sv_ld_elwidth_offs.S index 31ac3af..bb23a08 100644 --- a/isa/rv64ui/sv_ld_elwidth_offs.S +++ b/isa/rv64ui/sv_ld_elwidth_offs.S @@ -3,7 +3,7 @@ RVTEST_RV64U # Define TVM used by program. -#define SV_ELWIDTH_TEST( inst, vl, elwidth, wid1, wid2, \ +#define SV_ELWIDTH_TEST( inst, vl, wid1, wid2, \ testdata, expect1, expect2, expect3 ) \ \ la x12, testdata ; \ @@ -36,19 +36,19 @@ RVTEST_RV64U # Define TVM used by program. # Test code region. RVTEST_CODE_BEGIN # Start of test code. - SV_ELWIDTH_TEST( ld , 2, 8, SV_W_DFLT, SV_W_DFLT, testdata1, + SV_ELWIDTH_TEST( ld , 2, SV_W_DFLT, SV_W_DFLT, testdata1, 0x8979695949392919, 0x8777675747372717, 0xa5a5a5a5a5a5a5a5 ) - SV_ELWIDTH_TEST( ld , 3, 8, SV_W_DFLT, SV_W_DFLT, testdata1, + SV_ELWIDTH_TEST( ld , 3, SV_W_DFLT, SV_W_DFLT, testdata1, 0x8979695949392919, 0x8777675747372717, 0x8676665646362616 ) - SV_ELWIDTH_TEST( ld , 3, 8, SV_W_16BIT, SV_W_DFLT, testdata1, + SV_ELWIDTH_TEST( ld , 3, SV_W_16BIT, SV_W_DFLT, testdata1, 0x0000000000002919, 0x0000000000004939, 0x0000000000006959 ) - SV_ELWIDTH_TEST( ld , 5, 8, SV_W_16BIT, SV_W_32BIT, testdata1, + SV_ELWIDTH_TEST( ld , 5, SV_W_16BIT, SV_W_32BIT, testdata1, 0x0000493900002919, 0xffff897900006959, 0xa5a5a5a500002717 ) - SV_ELWIDTH_TEST( ld , 5, 8, SV_W_32BIT, SV_W_16BIT, testdata1, + SV_ELWIDTH_TEST( ld , 5, SV_W_32BIT, SV_W_16BIT, testdata1, 0x6757271769592919, 0xa5a5a5a5a5a52616, 0xa5a5a5a5a5a5a5a5 ) - SV_ELWIDTH_TEST( ld , 7, 8, SV_W_16BIT, SV_W_8BIT, testdata1, + SV_ELWIDTH_TEST( ld , 7, SV_W_16BIT, SV_W_8BIT, testdata1, 0xa557371779593919, 0xa5a5a5a5a5a5a5a5, 0xa5a5a5a5a5a5a5a5 ) - SV_ELWIDTH_TEST( ld , 11, 8, SV_W_8BIT, SV_W_16BIT, testdata1, + SV_ELWIDTH_TEST( ld , 11, SV_W_8BIT, SV_W_16BIT, testdata1, 0x0049003900290019, 0xff89007900690059, 0xa5a5003700270017 ) RVTEST_PASS # Signal success. fail: