From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 8 Mar 2021 12:07:50 +0000 (+0000)
Subject: correct comments in sv.add rc=1
X-Git-Tag: convert-csv-opcode-to-binary~86
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7408512c6e7674148ff9293c0ca5b29f74fb2bf8;p=soc.git

correct comments in sv.add rc=1
---

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 8761fdc4..92e8522a 100644
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -76,9 +76,10 @@ class SVP64ALUTestCase(TestAccumulatorBase):
                       initial_svstate=svstate)
 
     def case_4_sv_add_(self):
-        # adds:
-        #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
-        #       2 = 6 + 10  => 0x3334 = 0x2223 + 0x1111
+        # adds when Rc=1:                               TODO CRs higher up
+        #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
+        #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
+
         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'])
         lst = list(isa)
         print("listing", lst)