From: Michael Nolan Date: Tue, 5 May 2020 19:58:34 +0000 (-0400) Subject: Add rudimentary branch capability X-Git-Tag: div_pipeline~1379 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75f07eb9ef019356dfb7118482e8cab33d073678;p=soc.git Add rudimentary branch capability --- diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 81a294d2..03503330 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -121,7 +121,7 @@ class PC: self.NIA = self.CIA + SelectableInt(4, 64) def update(self, namespace): - self.CIA = self.NIA + self.CIA = namespace['NIA'].narrow(64) self.NIA = self.CIA + SelectableInt(4, 64) namespace['CIA'] = self.CIA namespace['NIA'] = self.NIA @@ -160,6 +160,7 @@ class ISACaller: 'NIA': self.pc.NIA, 'CIA': self.pc.CIA, 'CR': self.cr, + 'LR': self.undefined, 'undefined': self.undefined, } @@ -246,8 +247,8 @@ def inject(): context = args[0].namespace saved_values = func_globals.copy() # Shallow copy of dict. func_globals.update(context) - result = func(*args, **kwargs) + args[0].namespace = func_globals #exec (func.__code__, func_globals) #finally: diff --git a/src/soc/decoder/isa/test_caller.py b/src/soc/decoder/isa/test_caller.py index 0c5ec46a..5d4869fa 100644 --- a/src/soc/decoder/isa/test_caller.py +++ b/src/soc/decoder/isa/test_caller.py @@ -33,7 +33,11 @@ class DecoderTestCase(FHDLTestCase): gen = generator.generate_instructions() def process(): - for ins, code in zip(gen, generator.assembly.splitlines()): + instructions = list(zip(gen, generator.assembly.splitlines())) + + index = simulator.pc.CIA.value//4 + while index < len(instructions): + ins, code = instructions[index] print("0x{:X}".format(ins & 0xffffffff)) print(code) @@ -44,6 +48,7 @@ class DecoderTestCase(FHDLTestCase): yield Delay(1e-6) opname = code.split(' ')[0] yield from simulator.call(opname) + index = simulator.pc.CIA.value//4 sim.add_process(process) with sim.write_vcd("simulator.vcd", "simulator.gtkw", @@ -89,6 +94,18 @@ class DecoderTestCase(FHDLTestCase): self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64)) self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64)) + def test_branch(self): + lst = ["ba 0xc", # branch to line 4 + "addi 1, 0, 0x1234", # Should never execute + "ba 0x1000", # exit the program + "addi 2, 0, 0x1234", # line 4 + "ba 0x8"] # branch to line 3 + with Program(lst) as program: + sim = self.run_tst_program(program) + self.assertEqual(sim.pc.CIA, SelectableInt(0x1000, 64)) + self.assertEqual(sim.gpr(1), SelectableInt(0x0, 64)) + self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64)) + @unittest.skip("broken") # FIXME def test_mtcrf(self): for i in range(4): diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py index 922de376..abdf9940 100644 --- a/src/soc/decoder/pseudo/pywriter.py +++ b/src/soc/decoder/pseudo/pywriter.py @@ -64,6 +64,8 @@ class PyISAWriter(ISA): op_fname ="op_%s" % page.replace(".", "_") f.write(" @inject()\n") f.write(" def %s(%s):\n" % (op_fname, args)) + if 'NIA' in pycode: # HACK - TODO fix + f.write(" global NIA\n") pycode = pycode.split("\n") pycode = '\n'.join(map(lambda x: " %s" % x, pycode)) pycode = pycode.rstrip()