From: Luke Kenneth Casson Leighton Date: Fri, 26 Oct 2018 05:46:11 +0000 (+0100) Subject: add sv_add_elwidth unit test X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7606c58e26503856376b9b4af86d963e31ce9e58;p=riscv-tests.git add sv_add_elwidth unit test --- diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h index a480bd6..dccb784 100644 --- a/isa/macros/simplev/sv_test_macros.h +++ b/isa/macros/simplev/sv_test_macros.h @@ -12,11 +12,15 @@ csrrw x0, 0x4c8, x1 #define SET_SV_2CSRS( c1, c2 ) \ - li x1, c1 | ((c2)<<16); \ + li x1, c1 | ((c2)<<16U); \ + csrrw x0, 0x4c0, x1 + +#define SET_SV_3CSRS( c1, c2 , c3 ) \ + li x1, c1 | ((c2)<<16U) | ((c3)<<32U); \ csrrw x0, 0x4c0, x1 #define SET_SV_2PREDCSRS( c1, c2 ) \ - li x1, c1 | ((c2)<<16); \ + li x1, c1 | ((c2)<<16U); \ csrrw x0, 0x4c8, x1 #define CLR_SV_CSRS( ) csrrw x0, 0x4c0, 0 @@ -29,12 +33,16 @@ la x1, from; \ lw reg, offs(x1) +#define SV_LDD_DATA( reg, from, offs ) \ + la x1, from; \ + ld reg, offs(x1) + #define SV_FLD_DATA( reg, from, offs ) \ la x1, from; \ fld reg, offs(x1) #define TEST_SV_IMM( reg, imm ) \ - li t6, imm; \ + li t6, ((imm) & 0xffffffffffffffff); \ bne reg, t6, fail #define TEST_SV_FD( flags, freg, from, offs ) \ diff --git a/isa/rv64ui/Makefrag.sv b/isa/rv64ui/Makefrag.sv index ab4744d..aaa7353 100644 --- a/isa/rv64ui/Makefrag.sv +++ b/isa/rv64ui/Makefrag.sv @@ -8,6 +8,7 @@ rv64ui_sv_tests = \ sv_addi_scalar_src \ sv_addi_vector_vector \ sv_addi_predicated \ + sv_add_elwidth \ sv_beq \ rv64ui_p_tests = $(addprefix rv64ui-p-, $(rv64ui_sv_tests)) diff --git a/isa/rv64ui/sv_add_elwidth.S b/isa/rv64ui/sv_add_elwidth.S new file mode 100644 index 0000000..501be37 --- /dev/null +++ b/isa/rv64ui/sv_add_elwidth.S @@ -0,0 +1,71 @@ +#include "riscv_test.h" +#include "sv_test_macros.h" + +RVTEST_RV64U # Define TVM used by program. + +#define SV_ELWIDTH_TEST( wid1, wid2, wid3, expect1, expect2 ) \ + \ + SV_LDD_DATA( x2, testdata , 0); \ + SV_LDD_DATA( x3, testdata+8 , 0); \ + SV_LDD_DATA( x4, testdata+16, 0); \ + SV_LDD_DATA( x5, testdata+24, 0); \ + \ + li x28, 0; \ + li x29, 0; \ + \ + SET_SV_MVL( 2); \ + SET_SV_3CSRS( SV_REG_CSR( 1, 2, wid1, 2, 1), \ + SV_REG_CSR( 1, 4, wid2, 4, 1), \ + SV_REG_CSR( 1, 28, wid3, 28, 1)); \ + SET_SV_VL( 2); \ + \ + add x28, x2, x4; \ + \ + CLR_SV_CSRS(); \ + SET_SV_VL( 1); \ + SET_SV_MVL( 1); \ + \ + TEST_SV_IMM( x28, expect1); \ + TEST_SV_IMM( x29, expect2); \ + TEST_SV_IMM( x4, 0x0000005242322212); \ + TEST_SV_IMM( x5, 0x0000005141312111); + + +# SV test: vector-vector add +# +# sets up x3 and x4 with data, sets VL to 2, and carries out +# an "add 1 to x3". which actually means "add 1 to x3 *AND* add 1 to x4" + +# Test code region. +RVTEST_CODE_BEGIN # Start of test code. + + # + SV_ELWIDTH_TEST( 0, 0, 0, 0x000000ab8b6b4b2b, 0x000000aa8a6a4a2a ) + //SV_ELWIDTH_TEST( 0x2, 0, 0, 41, 43 ) + //SV_ELWIDTH_TEST( 0x3, 0, 0, 42, 43 ) + //SV_ELWIDTH_TEST( 0x0, 0, 0, 41, 42 ) + + RVTEST_PASS # Signal success. +fail: + RVTEST_FAIL +RVTEST_CODE_END # End of test code. + +# Input data section. +# This section is optional, and this data is NOT saved in the output. +.data + .align 3 +testdata: + .dword 0x0000005949392919 + .dword 0x0000005747372717 + .dword 0x0000005242322212 + .dword 0x0000005141312111 + +# Output data section. +RVTEST_DATA_BEGIN # Start of test output data region. + .align 3 +result: + .dword -1 + .dword -1 + .dword -1 +RVTEST_DATA_END # End of test output data region. +