From: Tobias Platen <tplaten@posteo.de>
Date: Mon, 13 Dec 2021 13:27:51 +0000 (+0100)
Subject: update old TestMicrowattMemoryPortInterface
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7610b5f37bfb71b630cfaba9c1eb278461cacb60;p=soc.git

update old TestMicrowattMemoryPortInterface
---

diff --git a/src/soc/experiment/test/test_mmu_dcache_pi.py b/src/soc/experiment/test/test_mmu_dcache_pi.py
index a4ad1dab..c2b76df5 100644
--- a/src/soc/experiment/test/test_mmu_dcache_pi.py
+++ b/src/soc/experiment/test/test_mmu_dcache_pi.py
@@ -85,18 +85,18 @@ class TestMicrowattMemoryPortInterface(PortInterfaceBase):
         self.mmu = mmu
         self.dcache = dcache
 
-    def set_wr_addr(self, m, addr, mask, misalign, msr_pr, is_dcbz):
+    def set_wr_addr(self, m, addr, mask, misalign, msr, is_dcbz):
         m.d.comb += self.dcache.d_in.addr.eq(addr)
         m.d.comb += self.mmu.l_in.addr.eq(addr)
         m.d.comb += self.mmu.l_in.load.eq(0)
-        m.d.comb += self.mmu.l_in.priv.eq(1) # TODO put msr_pr here
+        m.d.comb += self.mmu.l_in.priv.eq(~msr.pr) # TODO verify
         m.d.comb += self.mmu.l_in.valid.eq(1)
 
-    def set_rd_addr(self, m, addr, mask, misalign, msr_pr):
+    def set_rd_addr(self, m, addr, mask, misalign, msr):
         m.d.comb += self.dcache.d_in.addr.eq(addr)
         m.d.comb += self.mmu.l_in.addr.eq(addr)
         m.d.comb += self.mmu.l_in.load.eq(1)
-        m.d.comb += self.mmu.l_in.priv.eq(1) # TODO put msr_pr here
+        m.d.comb += self.mmu.l_in.priv.eq(~msr.pr) # TODO verify
         m.d.comb += self.mmu.l_in.valid.eq(1)
 
     def set_wr_data(self, m, data, wen):